// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  sysctrl_cfg_reg_offset_field.h
// Project line  :  ICT
// Department    :  ICT Processor Chipset Development Dep
// Author        :  xxx
// Version       :  1.0
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/19 15:49:11 Create file
// ******************************************************************************

#ifndef __SYSCTRL_CFG_REG_OFFSET_FIELD_H__
#define __SYSCTRL_CFG_REG_OFFSET_FIELD_H__

#define SYSCTRL_CFG_PLL0_FOUTVCOPD_LEN        1
#define SYSCTRL_CFG_PLL0_FOUTVCOPD_OFFSET     30
#define SYSCTRL_CFG_PLL0_FOUTPOSTDIVPD_LEN    1
#define SYSCTRL_CFG_PLL0_FOUTPOSTDIVPD_OFFSET 29
#define SYSCTRL_CFG_PLL0_FOUT4PHASEPD_LEN     1
#define SYSCTRL_CFG_PLL0_FOUT4PHASEPD_OFFSET  28
#define SYSCTRL_CFG_PLL0_DACPD_LEN            1
#define SYSCTRL_CFG_PLL0_DACPD_OFFSET         27
#define SYSCTRL_CFG_PLL0_DSMPD_LEN            1
#define SYSCTRL_CFG_PLL0_DSMPD_OFFSET         26
#define SYSCTRL_CFG_PLL0_PD_LEN               1
#define SYSCTRL_CFG_PLL0_PD_OFFSET            25
#define SYSCTRL_CFG_PLL0_BYPASS_LEN           1
#define SYSCTRL_CFG_PLL0_BYPASS_OFFSET        24
#define SYSCTRL_CFG_PLL0_POSTDIV2_LEN         3
#define SYSCTRL_CFG_PLL0_POSTDIV2_OFFSET      21
#define SYSCTRL_CFG_PLL0_POSTDIV1_LEN         3
#define SYSCTRL_CFG_PLL0_POSTDIV1_OFFSET      18
#define SYSCTRL_CFG_PLL0_FBDIV_LEN            12
#define SYSCTRL_CFG_PLL0_FBDIV_OFFSET         6
#define SYSCTRL_CFG_PLL0_REFDIV_LEN           6
#define SYSCTRL_CFG_PLL0_REFDIV_OFFSET        0

#define SYSCTRL_CFG_PLL0_FRAC_LEN    24
#define SYSCTRL_CFG_PLL0_FRAC_OFFSET 0

#define SYSCTRL_CFG_PLL1_FOUTVCOPD_LEN        1
#define SYSCTRL_CFG_PLL1_FOUTVCOPD_OFFSET     30
#define SYSCTRL_CFG_PLL1_FOUTPOSTDIVPD_LEN    1
#define SYSCTRL_CFG_PLL1_FOUTPOSTDIVPD_OFFSET 29
#define SYSCTRL_CFG_PLL1_FOUT4PHASEPD_LEN     1
#define SYSCTRL_CFG_PLL1_FOUT4PHASEPD_OFFSET  28
#define SYSCTRL_CFG_PLL1_DACPD_LEN            1
#define SYSCTRL_CFG_PLL1_DACPD_OFFSET         27
#define SYSCTRL_CFG_PLL1_DSMPD_LEN            1
#define SYSCTRL_CFG_PLL1_DSMPD_OFFSET         26
#define SYSCTRL_CFG_PLL1_PD_LEN               1
#define SYSCTRL_CFG_PLL1_PD_OFFSET            25
#define SYSCTRL_CFG_PLL1_BYPASS_LEN           1
#define SYSCTRL_CFG_PLL1_BYPASS_OFFSET        24
#define SYSCTRL_CFG_PLL1_POSTDIV2_LEN         3
#define SYSCTRL_CFG_PLL1_POSTDIV2_OFFSET      21
#define SYSCTRL_CFG_PLL1_POSTDIV1_LEN         3
#define SYSCTRL_CFG_PLL1_POSTDIV1_OFFSET      18
#define SYSCTRL_CFG_PLL1_FBDIV_LEN            12
#define SYSCTRL_CFG_PLL1_FBDIV_OFFSET         6
#define SYSCTRL_CFG_PLL1_REFDIV_LEN           6
#define SYSCTRL_CFG_PLL1_REFDIV_OFFSET        0

#define SYSCTRL_CFG_PLL1_FRAC_LEN    24
#define SYSCTRL_CFG_PLL1_FRAC_OFFSET 0

#define SYSCTRL_CFG_PLL2_FOUTVCOPD_LEN        1
#define SYSCTRL_CFG_PLL2_FOUTVCOPD_OFFSET     30
#define SYSCTRL_CFG_PLL2_FOUTPOSTDIVPD_LEN    1
#define SYSCTRL_CFG_PLL2_FOUTPOSTDIVPD_OFFSET 29
#define SYSCTRL_CFG_PLL2_FOUT4PHASEPD_LEN     1
#define SYSCTRL_CFG_PLL2_FOUT4PHASEPD_OFFSET  28
#define SYSCTRL_CFG_PLL2_DACPD_LEN            1
#define SYSCTRL_CFG_PLL2_DACPD_OFFSET         27
#define SYSCTRL_CFG_PLL2_DSMPD_LEN            1
#define SYSCTRL_CFG_PLL2_DSMPD_OFFSET         26
#define SYSCTRL_CFG_PLL2_PD_LEN               1
#define SYSCTRL_CFG_PLL2_PD_OFFSET            25
#define SYSCTRL_CFG_PLL2_BYPASS_LEN           1
#define SYSCTRL_CFG_PLL2_BYPASS_OFFSET        24
#define SYSCTRL_CFG_PLL2_POSTDIV2_LEN         3
#define SYSCTRL_CFG_PLL2_POSTDIV2_OFFSET      21
#define SYSCTRL_CFG_PLL2_POSTDIV1_LEN         3
#define SYSCTRL_CFG_PLL2_POSTDIV1_OFFSET      18
#define SYSCTRL_CFG_PLL2_FBDIV_LEN            12
#define SYSCTRL_CFG_PLL2_FBDIV_OFFSET         6
#define SYSCTRL_CFG_PLL2_REFDIV_LEN           6
#define SYSCTRL_CFG_PLL2_REFDIV_OFFSET        0

#define SYSCTRL_CFG_PLL2_FRAC_LEN    24
#define SYSCTRL_CFG_PLL2_FRAC_OFFSET 0

#define SYSCTRL_CFG_PLL3_FOUTVCOPD_LEN        1
#define SYSCTRL_CFG_PLL3_FOUTVCOPD_OFFSET     30
#define SYSCTRL_CFG_PLL3_FOUTPOSTDIVPD_LEN    1
#define SYSCTRL_CFG_PLL3_FOUTPOSTDIVPD_OFFSET 29
#define SYSCTRL_CFG_PLL3_FOUT4PHASEPD_LEN     1
#define SYSCTRL_CFG_PLL3_FOUT4PHASEPD_OFFSET  28
#define SYSCTRL_CFG_PLL3_DACPD_LEN            1
#define SYSCTRL_CFG_PLL3_DACPD_OFFSET         27
#define SYSCTRL_CFG_PLL3_DSMPD_LEN            1
#define SYSCTRL_CFG_PLL3_DSMPD_OFFSET         26
#define SYSCTRL_CFG_PLL3_PD_LEN               1
#define SYSCTRL_CFG_PLL3_PD_OFFSET            25
#define SYSCTRL_CFG_PLL3_BYPASS_LEN           1
#define SYSCTRL_CFG_PLL3_BYPASS_OFFSET        24
#define SYSCTRL_CFG_PLL3_POSTDIV2_LEN         3
#define SYSCTRL_CFG_PLL3_POSTDIV2_OFFSET      21
#define SYSCTRL_CFG_PLL3_POSTDIV1_LEN         3
#define SYSCTRL_CFG_PLL3_POSTDIV1_OFFSET      18
#define SYSCTRL_CFG_PLL3_FBDIV_LEN            12
#define SYSCTRL_CFG_PLL3_FBDIV_OFFSET         6
#define SYSCTRL_CFG_PLL3_REFDIV_LEN           6
#define SYSCTRL_CFG_PLL3_REFDIV_OFFSET        0

#define SYSCTRL_CFG_PLL3_FRAC_LEN    24
#define SYSCTRL_CFG_PLL3_FRAC_OFFSET 0

#define SYSCTRL_CFG_PLL4_FOUTVCOPD_LEN        1
#define SYSCTRL_CFG_PLL4_FOUTVCOPD_OFFSET     30
#define SYSCTRL_CFG_PLL4_FOUTPOSTDIVPD_LEN    1
#define SYSCTRL_CFG_PLL4_FOUTPOSTDIVPD_OFFSET 29
#define SYSCTRL_CFG_PLL4_FOUT4PHASEPD_LEN     1
#define SYSCTRL_CFG_PLL4_FOUT4PHASEPD_OFFSET  28
#define SYSCTRL_CFG_PLL4_DACPD_LEN            1
#define SYSCTRL_CFG_PLL4_DACPD_OFFSET         27
#define SYSCTRL_CFG_PLL4_DSMPD_LEN            1
#define SYSCTRL_CFG_PLL4_DSMPD_OFFSET         26
#define SYSCTRL_CFG_PLL4_PD_LEN               1
#define SYSCTRL_CFG_PLL4_PD_OFFSET            25
#define SYSCTRL_CFG_PLL4_BYPASS_LEN           1
#define SYSCTRL_CFG_PLL4_BYPASS_OFFSET        24
#define SYSCTRL_CFG_PLL4_POSTDIV2_LEN         3
#define SYSCTRL_CFG_PLL4_POSTDIV2_OFFSET      21
#define SYSCTRL_CFG_PLL4_POSTDIV1_LEN         3
#define SYSCTRL_CFG_PLL4_POSTDIV1_OFFSET      18
#define SYSCTRL_CFG_PLL4_FBDIV_LEN            12
#define SYSCTRL_CFG_PLL4_FBDIV_OFFSET         6
#define SYSCTRL_CFG_PLL4_REFDIV_LEN           6
#define SYSCTRL_CFG_PLL4_REFDIV_OFFSET        0

#define SYSCTRL_CFG_PLL4_FRAC_LEN    24
#define SYSCTRL_CFG_PLL4_FRAC_OFFSET 0

#define SYSCTRL_CFG_PLL5_FOUTVCOPD_LEN        1
#define SYSCTRL_CFG_PLL5_FOUTVCOPD_OFFSET     30
#define SYSCTRL_CFG_PLL5_FOUTPOSTDIVPD_LEN    1
#define SYSCTRL_CFG_PLL5_FOUTPOSTDIVPD_OFFSET 29
#define SYSCTRL_CFG_PLL5_FOUT4PHASEPD_LEN     1
#define SYSCTRL_CFG_PLL5_FOUT4PHASEPD_OFFSET  28
#define SYSCTRL_CFG_PLL5_DACPD_LEN            1
#define SYSCTRL_CFG_PLL5_DACPD_OFFSET         27
#define SYSCTRL_CFG_PLL5_DSMPD_LEN            1
#define SYSCTRL_CFG_PLL5_DSMPD_OFFSET         26
#define SYSCTRL_CFG_PLL5_PD_LEN               1
#define SYSCTRL_CFG_PLL5_PD_OFFSET            25
#define SYSCTRL_CFG_PLL5_BYPASS_LEN           1
#define SYSCTRL_CFG_PLL5_BYPASS_OFFSET        24
#define SYSCTRL_CFG_PLL5_POSTDIV2_LEN         3
#define SYSCTRL_CFG_PLL5_POSTDIV2_OFFSET      21
#define SYSCTRL_CFG_PLL5_POSTDIV1_LEN         3
#define SYSCTRL_CFG_PLL5_POSTDIV1_OFFSET      18
#define SYSCTRL_CFG_PLL5_FBDIV_LEN            12
#define SYSCTRL_CFG_PLL5_FBDIV_OFFSET         6
#define SYSCTRL_CFG_PLL5_REFDIV_LEN           6
#define SYSCTRL_CFG_PLL5_REFDIV_OFFSET        0

#define SYSCTRL_CFG_PLL5_FRAC_LEN    24
#define SYSCTRL_CFG_PLL5_FRAC_OFFSET 0

#define SYSCTRL_CFG_PLL5_BYPASS_EXTERNAL_N_LEN    1
#define SYSCTRL_CFG_PLL5_BYPASS_EXTERNAL_N_OFFSET 5
#define SYSCTRL_CFG_PLL4_BYPASS_EXTERNAL_N_LEN    1
#define SYSCTRL_CFG_PLL4_BYPASS_EXTERNAL_N_OFFSET 4
#define SYSCTRL_CFG_PLL3_BYPASS_EXTERNAL_N_LEN    1
#define SYSCTRL_CFG_PLL3_BYPASS_EXTERNAL_N_OFFSET 3
#define SYSCTRL_CFG_PLL2_BYPASS_EXTERNAL_N_LEN    1
#define SYSCTRL_CFG_PLL2_BYPASS_EXTERNAL_N_OFFSET 2
#define SYSCTRL_CFG_PLL1_BYPASS_EXTERNAL_N_LEN    1
#define SYSCTRL_CFG_PLL1_BYPASS_EXTERNAL_N_OFFSET 1
#define SYSCTRL_CFG_PLL0_BYPASS_EXTERNAL_N_LEN    1
#define SYSCTRL_CFG_PLL0_BYPASS_EXTERNAL_N_OFFSET 0

#define SYSCTRL_CFG_PLL5_PERI_MODE_LEN    1
#define SYSCTRL_CFG_PLL5_PERI_MODE_OFFSET 5
#define SYSCTRL_CFG_PLL4_PERI_MODE_LEN    1
#define SYSCTRL_CFG_PLL4_PERI_MODE_OFFSET 4
#define SYSCTRL_CFG_PLL3_PERI_MODE_LEN    1
#define SYSCTRL_CFG_PLL3_PERI_MODE_OFFSET 3
#define SYSCTRL_CFG_PLL2_PERI_MODE_LEN    1
#define SYSCTRL_CFG_PLL2_PERI_MODE_OFFSET 2
#define SYSCTRL_CFG_PLL1_PERI_MODE_LEN    1
#define SYSCTRL_CFG_PLL1_PERI_MODE_OFFSET 1
#define SYSCTRL_CFG_PLL0_PERI_MODE_LEN    1
#define SYSCTRL_CFG_PLL0_PERI_MODE_OFFSET 0

#define SYSCTRL_CFG_PLL_TIME_LEN     25
#define SYSCTRL_CFG_PLL_TIME_OFFSET  3
#define SYSCTRL_CFG_PLL_EN_SW_LEN    1
#define SYSCTRL_CFG_PLL_EN_SW_OFFSET 1
#define SYSCTRL_CFG_PLL_OVER_LEN     1
#define SYSCTRL_CFG_PLL_OVER_OFFSET  0

#define SYSCTRL_CFG_MODECTRL_LEN    3
#define SYSCTRL_CFG_MODECTRL_OFFSET 0

#define SYSCTRL_CFG_HPM_CLK_SEL_LEN    1
#define SYSCTRL_CFG_HPM_CLK_SEL_OFFSET 0

#define SYSCTRL_CFG_FUNC_MBIST_CLK_SEL_LEN    1
#define SYSCTRL_CFG_FUNC_MBIST_CLK_SEL_OFFSET 0

#define SYSCTRL_CFG_PLL0_OUT_CLK_SEL_LEN    1
#define SYSCTRL_CFG_PLL0_OUT_CLK_SEL_OFFSET 0

#define SYSCTRL_CFG_ALL_SCAN_SYS_INT_LEN    1
#define SYSCTRL_CFG_ALL_SCAN_SYS_INT_OFFSET 0

#define SYSCTRL_CFG_SYS_SOFT_RST_LEN    32
#define SYSCTRL_CFG_SYS_SOFT_RST_OFFSET 0

#define SYSCTRL_CFG_PORN_ENABLE_LEN    1
#define SYSCTRL_CFG_PORN_ENABLE_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_SDMA_LEN    1
#define SYSCTRL_CFG_ICG_EN_SDMA_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_SDMA_LEN    1
#define SYSCTRL_CFG_ICG_DIS_SDMA_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_FTE_LEN    1
#define SYSCTRL_CFG_ICG_EN_FTE_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_FTE_LEN    1
#define SYSCTRL_CFG_ICG_DIS_FTE_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_SMMU_LEN    1
#define SYSCTRL_CFG_ICG_EN_SMMU_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_SMMU_LEN    1
#define SYSCTRL_CFG_ICG_DIS_SMMU_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_RGMII_BUS_LEN        1
#define SYSCTRL_CFG_ICG_EN_RGMII_BUS_OFFSET     5
#define SYSCTRL_CFG_ICG_EN_RGMII_GSF_AXI_LEN    1
#define SYSCTRL_CFG_ICG_EN_RGMII_GSF_AXI_OFFSET 4
#define SYSCTRL_CFG_ICG_EN_RGMII_SYS_PUB_LEN    1
#define SYSCTRL_CFG_ICG_EN_RGMII_SYS_PUB_OFFSET 3
#define SYSCTRL_CFG_ICG_EN_RGMII_GSF_125_LEN    1
#define SYSCTRL_CFG_ICG_EN_RGMII_GSF_125_OFFSET 2
#define SYSCTRL_CFG_ICG_EN_RGMII_CRG_125_LEN    1
#define SYSCTRL_CFG_ICG_EN_RGMII_CRG_125_OFFSET 1
#define SYSCTRL_CFG_ICG_EN_RGMII_RX_LEN         1
#define SYSCTRL_CFG_ICG_EN_RGMII_RX_OFFSET      0

#define SYSCTRL_CFG_ICG_DIS_RGMII_BUS_LEN        1
#define SYSCTRL_CFG_ICG_DIS_RGMII_BUS_OFFSET     5
#define SYSCTRL_CFG_ICG_DIS_RGMII_GSF_AXI_LEN    1
#define SYSCTRL_CFG_ICG_DIS_RGMII_GSF_AXI_OFFSET 4
#define SYSCTRL_CFG_ICG_DIS_RGMII_SYS_PUB_LEN    1
#define SYSCTRL_CFG_ICG_DIS_RGMII_SYS_PUB_OFFSET 3
#define SYSCTRL_CFG_ICG_DIS_RGMII_GSF_125_LEN    1
#define SYSCTRL_CFG_ICG_DIS_RGMII_GSF_125_OFFSET 2
#define SYSCTRL_CFG_ICG_DIS_RGMII_CRG_125_LEN    1
#define SYSCTRL_CFG_ICG_DIS_RGMII_CRG_125_OFFSET 1
#define SYSCTRL_CFG_ICG_DIS_RGMII_RX_LEN         1
#define SYSCTRL_CFG_ICG_DIS_RGMII_RX_OFFSET      0

#define SYSCTRL_CFG_ICG_EN_USB_BUS_EARLY_LEN    1
#define SYSCTRL_CFG_ICG_EN_USB_BUS_EARLY_OFFSET 3
#define SYSCTRL_CFG_ICG_EN_USB_SUSPEND_LEN      1
#define SYSCTRL_CFG_ICG_EN_USB_SUSPEND_OFFSET   2
#define SYSCTRL_CFG_ICG_EN_USB_PIPE3P_LEN       1
#define SYSCTRL_CFG_ICG_EN_USB_PIPE3P_OFFSET    1
#define SYSCTRL_CFG_ICG_EN_USB_UTMI_LEN         1
#define SYSCTRL_CFG_ICG_EN_USB_UTMI_OFFSET      0

#define SYSCTRL_CFG_ICG_DIS_USB_BUS_EARLY_LEN    1
#define SYSCTRL_CFG_ICG_DIS_USB_BUS_EARLY_OFFSET 3
#define SYSCTRL_CFG_ICG_DIS_USB_SUSPEND_LEN      1
#define SYSCTRL_CFG_ICG_DIS_USB_SUSPEND_OFFSET   2
#define SYSCTRL_CFG_ICG_DIS_USB_PIPE3P_LEN       1
#define SYSCTRL_CFG_ICG_DIS_USB_PIPE3P_OFFSET    1
#define SYSCTRL_CFG_ICG_DIS_USB_UTMI_LEN         1
#define SYSCTRL_CFG_ICG_DIS_USB_UTMI_OFFSET      0

#define SYSCTRL_CFG_ICG_EN_SYS_COUNTER_LEN    1
#define SYSCTRL_CFG_ICG_EN_SYS_COUNTER_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_SYS_COUNTER_LEN    1
#define SYSCTRL_CFG_ICG_DIS_SYS_COUNTER_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_DDR_LEN    4
#define SYSCTRL_CFG_ICG_EN_DDR_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_DDR_LEN    4
#define SYSCTRL_CFG_ICG_DIS_DDR_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_HHA1_LEN    1
#define SYSCTRL_CFG_ICG_EN_HHA1_OFFSET 1

#define SYSCTRL_CFG_ICG_DIS_HHA1_LEN    1
#define SYSCTRL_CFG_ICG_DIS_HHA1_OFFSET 1

#define SYSCTRL_CFG_ICG_EN_MN1_LEN    1
#define SYSCTRL_CFG_ICG_EN_MN1_OFFSET 1

#define SYSCTRL_CFG_ICG_DIS_MN1_LEN    1
#define SYSCTRL_CFG_ICG_DIS_MN1_OFFSET 1

#define SYSCTRL_CFG_ICG_EN_EXMBIST_CFG_LEN     1
#define SYSCTRL_CFG_ICG_EN_EXMBIST_CFG_OFFSET  1
#define SYSCTRL_CFG_ICG_EN_EXMBIST_ACLK_LEN    1
#define SYSCTRL_CFG_ICG_EN_EXMBIST_ACLK_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_EXMBIST_CFG_LEN     1
#define SYSCTRL_CFG_ICG_DIS_EXMBIST_CFG_OFFSET  1
#define SYSCTRL_CFG_ICG_DIS_EXMBIST_ACLK_LEN    1
#define SYSCTRL_CFG_ICG_DIS_EXMBIST_ACLK_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_DUM_APB_LEN    1
#define SYSCTRL_CFG_ICG_EN_DUM_APB_OFFSET 4
#define SYSCTRL_CFG_ICG_EN_P2P_M_LEN      1
#define SYSCTRL_CFG_ICG_EN_P2P_M_OFFSET   2

#define SYSCTRL_CFG_ICG_DIS_DUM_APB_LEN    1
#define SYSCTRL_CFG_ICG_DIS_DUM_APB_OFFSET 4
#define SYSCTRL_CFG_ICG_DIS_P2P_M_LEN      1
#define SYSCTRL_CFG_ICG_DIS_P2P_M_OFFSET   2

#define SYSCTRL_CFG_ICG_EN_PROBE_LEN    1
#define SYSCTRL_CFG_ICG_EN_PROBE_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_PROBE_LEN    1
#define SYSCTRL_CFG_ICG_DIS_PROBE_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_LLC_LEN    1
#define SYSCTRL_CFG_ICG_EN_LLC_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_LLC_LEN    1
#define SYSCTRL_CFG_ICG_DIS_LLC_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_L2BUFF1_LEN    1
#define SYSCTRL_CFG_ICG_EN_L2BUFF1_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_L2BUFF1_LEN    1
#define SYSCTRL_CFG_ICG_DIS_L2BUFF1_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_PIPE_LEN            4
#define SYSCTRL_CFG_ICG_EN_PIPE_OFFSET         5
#define SYSCTRL_CFG_ICG_EN_PHY_JTAG_TCK_LEN    1
#define SYSCTRL_CFG_ICG_EN_PHY_JTAG_TCK_OFFSET 4
#define SYSCTRL_CFG_ICG_EN_PHY_CR_PARA_LEN     1
#define SYSCTRL_CFG_ICG_EN_PHY_CR_PARA_OFFSET  3

#define SYSCTRL_CFG_ICG_DIS_PIPE_LEN            4
#define SYSCTRL_CFG_ICG_DIS_PIPE_OFFSET         5
#define SYSCTRL_CFG_ICG_DIS_PHY_JTAG_TCK_LEN    1
#define SYSCTRL_CFG_ICG_DIS_PHY_JTAG_TCK_OFFSET 4
#define SYSCTRL_CFG_ICG_DIS_PHY_CR_PARA_LEN     1
#define SYSCTRL_CFG_ICG_DIS_PHY_CR_PARA_OFFSET  3

#define SYSCTRL_CFG_ICG_EN_I2C_LEN    1
#define SYSCTRL_CFG_ICG_EN_I2C_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_I2C_LEN    1
#define SYSCTRL_CFG_ICG_DIS_I2C_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_TIMER_LEN    1
#define SYSCTRL_CFG_ICG_EN_TIMER_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_TIMER_LEN    1
#define SYSCTRL_CFG_ICG_DIS_TIMER_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_GPIO_LEN    2
#define SYSCTRL_CFG_ICG_EN_GPIO_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_GPIO_LEN    2
#define SYSCTRL_CFG_ICG_DIS_GPIO_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_SFC_BUS_LEN    1
#define SYSCTRL_CFG_ICG_EN_SFC_BUS_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_SFC_BUS_LEN    1
#define SYSCTRL_CFG_ICG_DIS_SFC_BUS_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_REF_LEN    1
#define SYSCTRL_CFG_ICG_EN_REF_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_REF_LEN    1
#define SYSCTRL_CFG_ICG_DIS_REF_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_GPIO_DB_LEN    1
#define SYSCTRL_CFG_ICG_EN_GPIO_DB_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_GPIO_DB_LEN    1
#define SYSCTRL_CFG_ICG_DIS_GPIO_DB_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_DJTAG_LEN    1
#define SYSCTRL_CFG_ICG_EN_DJTAG_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_DJTAG_LEN    1
#define SYSCTRL_CFG_ICG_DIS_DJTAG_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_FUNC_MBIST_LEN    1
#define SYSCTRL_CFG_ICG_EN_FUNC_MBIST_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_FUNC_MBIST_LEN    1
#define SYSCTRL_CFG_ICG_DIS_FUNC_MBIST_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_HPM_LEN    1
#define SYSCTRL_CFG_ICG_EN_HPM_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_HPM_LEN    1
#define SYSCTRL_CFG_ICG_DIS_HPM_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_ULTRASOC_LEN    1
#define SYSCTRL_CFG_ICG_EN_ULTRASOC_OFFSET 1
#define SYSCTRL_CFG_ICG_EN_CHIE_MON_LEN    1
#define SYSCTRL_CFG_ICG_EN_CHIE_MON_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_ULTRASOC_LEN    1
#define SYSCTRL_CFG_ICG_DIS_ULTRASOC_OFFSET 1
#define SYSCTRL_CFG_ICG_DIS_CHIE_MON_LEN    1
#define SYSCTRL_CFG_ICG_DIS_CHIE_MON_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_SPMI_LEN    1
#define SYSCTRL_CFG_ICG_EN_SPMI_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_SPMI_LEN    1
#define SYSCTRL_CFG_ICG_DIS_SPMI_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_PWM_8K_LEN    1
#define SYSCTRL_CFG_ICG_EN_PWM_8K_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_PWM_8K_LEN    1
#define SYSCTRL_CFG_ICG_DIS_PWM_8K_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_TIMESTAMP_LEN    1
#define SYSCTRL_CFG_ICG_EN_TIMESTAMP_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_TIMESTAMP_LEN    1
#define SYSCTRL_CFG_ICG_DIS_TIMESTAMP_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_MBIST_L2BUFF1_LEN    1
#define SYSCTRL_CFG_ICG_EN_MBIST_L2BUFF1_OFFSET 1
#define SYSCTRL_CFG_ICG_EN_MBIST_L2BUFF0_LEN    1
#define SYSCTRL_CFG_ICG_EN_MBIST_L2BUFF0_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_MBIST_L2BUFF1_LEN    1
#define SYSCTRL_CFG_ICG_DIS_MBIST_L2BUFF1_OFFSET 1
#define SYSCTRL_CFG_ICG_DIS_MBIST_L2BUFF0_LEN    1
#define SYSCTRL_CFG_ICG_DIS_MBIST_L2BUFF0_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_SRC_AI1_LEN    1
#define SYSCTRL_CFG_ICG_EN_SRC_AI1_OFFSET 1
#define SYSCTRL_CFG_ICG_EN_SRC_AI0_LEN    1
#define SYSCTRL_CFG_ICG_EN_SRC_AI0_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_SRC_AI1_LEN    1
#define SYSCTRL_CFG_ICG_DIS_SRC_AI1_OFFSET 1
#define SYSCTRL_CFG_ICG_DIS_SRC_AI0_LEN    1
#define SYSCTRL_CFG_ICG_DIS_SRC_AI0_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_GIC_CPU_ASYN_LEN    1
#define SYSCTRL_CFG_ICG_EN_GIC_CPU_ASYN_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_GIC_CPU_ASYN_LEN    1
#define SYSCTRL_CFG_ICG_DIS_GIC_CPU_ASYN_OFFSET 0

#define SYSCTRL_CFG_ICG_EN_CRS_ASYN_LEN    1
#define SYSCTRL_CFG_ICG_EN_CRS_ASYN_OFFSET 0

#define SYSCTRL_CFG_ICG_DIS_CRS_ASYN_LEN    1
#define SYSCTRL_CFG_ICG_DIS_CRS_ASYN_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_SDMA_LEN    1
#define SYSCTRL_CFG_SRST_REQ_SDMA_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_SDMA_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_SDMA_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_FTE_LEN    1
#define SYSCTRL_CFG_SRST_REQ_FTE_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_FTE_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_FTE_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_USBPHY_PORT_LEN     1
#define SYSCTRL_CFG_SRST_REQ_USBPHY_PORT_OFFSET  3
#define SYSCTRL_CFG_SRST_REQ_USB_VCC_LEN         1
#define SYSCTRL_CFG_SRST_REQ_USB_VCC_OFFSET      2
#define SYSCTRL_CFG_SRST_REQ_USBPHY_PIPE0_LEN    1
#define SYSCTRL_CFG_SRST_REQ_USBPHY_PIPE0_OFFSET 1
#define SYSCTRL_CFG_SRST_REQ_USBPHY_LEN          1
#define SYSCTRL_CFG_SRST_REQ_USBPHY_OFFSET       0

#define SYSCTRL_CFG_SRST_DREQ_USBPHY_PORT_LEN     1
#define SYSCTRL_CFG_SRST_DREQ_USBPHY_PORT_OFFSET  3
#define SYSCTRL_CFG_SRST_DREQ_USB_VCC_LEN         1
#define SYSCTRL_CFG_SRST_DREQ_USB_VCC_OFFSET      2
#define SYSCTRL_CFG_SRST_DREQ_USBPHY_PIPE0_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_USBPHY_PIPE0_OFFSET 1
#define SYSCTRL_CFG_SRST_DREQ_USBPHY_LEN          1
#define SYSCTRL_CFG_SRST_DREQ_USBPHY_OFFSET       0

#define SYSCTRL_CFG_SRST_REQ_RGMII_GSF_LEN       1
#define SYSCTRL_CFG_SRST_REQ_RGMII_GSF_OFFSET    1
#define SYSCTRL_CFG_SRST_REQ_RGMII_MAC_IF_LEN    1
#define SYSCTRL_CFG_SRST_REQ_RGMII_MAC_IF_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_RGMII_GSF_LEN       1
#define SYSCTRL_CFG_SRST_DREQ_RGMII_GSF_OFFSET    1
#define SYSCTRL_CFG_SRST_DREQ_RGMII_MAC_IF_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_RGMII_MAC_IF_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_SYS_COUNTER_LEN    1
#define SYSCTRL_CFG_SRST_REQ_SYS_COUNTER_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_SYS_COUNTER_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_SYS_COUNTER_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_DDRC_LEN    4
#define SYSCTRL_CFG_SRST_REQ_DDRC_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_DDRC_LEN    4
#define SYSCTRL_CFG_SRST_DREQ_DDRC_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_HHA1_LEN    1
#define SYSCTRL_CFG_SRST_REQ_HHA1_OFFSET 1

#define SYSCTRL_CFG_SRST_DREQ_HHA1_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_HHA1_OFFSET 1

#define SYSCTRL_CFG_SRST_REQ_MN1_LEN    1
#define SYSCTRL_CFG_SRST_REQ_MN1_OFFSET 1

#define SYSCTRL_CFG_SRST_DREQ_MN1_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_MN1_OFFSET 1

#define SYSCTRL_CFG_SRST_REQ_EXMBIST_ARESET_LEN    1
#define SYSCTRL_CFG_SRST_REQ_EXMBIST_ARESET_OFFSET 1
#define SYSCTRL_CFG_SRST_REQ_EXMBIST_LEN           1
#define SYSCTRL_CFG_SRST_REQ_EXMBIST_OFFSET        0

#define SYSCTRL_CFG_SRST_DREQ_EXMBIST_ARESET_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_EXMBIST_ARESET_OFFSET 1
#define SYSCTRL_CFG_SRST_DREQ_EXMBIST_LEN           1
#define SYSCTRL_CFG_SRST_DREQ_EXMBIST_OFFSET        0

#define SYSCTRL_CFG_SRST_REQ_DUM_LEN      1
#define SYSCTRL_CFG_SRST_REQ_DUM_OFFSET   4
#define SYSCTRL_CFG_SRST_REQ_P2P_M_LEN    1
#define SYSCTRL_CFG_SRST_REQ_P2P_M_OFFSET 2

#define SYSCTRL_CFG_SRST_DREQ_DUM_LEN      1
#define SYSCTRL_CFG_SRST_DREQ_DUM_OFFSET   4
#define SYSCTRL_CFG_SRST_DREQ_P2P_M_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_P2P_M_OFFSET 2

#define SYSCTRL_CFG_SRST_REQ_LLC_LEN    1
#define SYSCTRL_CFG_SRST_REQ_LLC_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_LLC_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_LLC_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_L2BUFF1_LEN    1
#define SYSCTRL_CFG_SRST_REQ_L2BUFF1_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_L2BUFF1_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_L2BUFF1_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_PCIE_PHY_LEN    1
#define SYSCTRL_CFG_SRST_REQ_PCIE_PHY_OFFSET 3
#define SYSCTRL_CFG_SRST_REQ_POR_PCIE_LEN    1
#define SYSCTRL_CFG_SRST_REQ_POR_PCIE_OFFSET 1
#define SYSCTRL_CFG_SRST_REQ_PCIE_LEN        1
#define SYSCTRL_CFG_SRST_REQ_PCIE_OFFSET     0

#define SYSCTRL_CFG_SRST_DREQ_PCIE_PHY_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_PCIE_PHY_OFFSET 3
#define SYSCTRL_CFG_SRST_DREQ_POR_PCIE_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_POR_PCIE_OFFSET 1
#define SYSCTRL_CFG_SRST_DREQ_PCIE_LEN        1
#define SYSCTRL_CFG_SRST_DREQ_PCIE_OFFSET     0

#define SYSCTRL_CFG_SRST_REQ_I2C_LEN    1
#define SYSCTRL_CFG_SRST_REQ_I2C_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_I2C_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_I2C_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_TIMER_LEN    1
#define SYSCTRL_CFG_SRST_REQ_TIMER_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_TIMER_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_TIMER_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_GPIO_LEN    2
#define SYSCTRL_CFG_SRST_REQ_GPIO_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_GPIO_LEN    2
#define SYSCTRL_CFG_SRST_DREQ_GPIO_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_SPMI_LEN    1
#define SYSCTRL_CFG_SRST_REQ_SPMI_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_SPMI_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_SPMI_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_USB_UTMI_LEN    1
#define SYSCTRL_CFG_SRST_REQ_USB_UTMI_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_USB_UTMI_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_USB_UTMI_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_ULTRASOC_LEN    1
#define SYSCTRL_CFG_SRST_REQ_ULTRASOC_OFFSET 1
#define SYSCTRL_CFG_SRST_REQ_CHIE_MON_LEN    1
#define SYSCTRL_CFG_SRST_REQ_CHIE_MON_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_ULTRASOC_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_ULTRASOC_OFFSET 1
#define SYSCTRL_CFG_SRST_DREQ_CHIE_MON_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_CHIE_MON_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_CPM1_LEN    1
#define SYSCTRL_CFG_SRST_REQ_CPM1_OFFSET 1
#define SYSCTRL_CFG_SRST_REQ_CPM0_LEN    1
#define SYSCTRL_CFG_SRST_REQ_CPM0_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_CPM1_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_CPM1_OFFSET 1
#define SYSCTRL_CFG_SRST_DREQ_CPM0_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_CPM0_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_SVFD1_LEN    1
#define SYSCTRL_CFG_SRST_REQ_SVFD1_OFFSET 1
#define SYSCTRL_CFG_SRST_REQ_SVFD0_LEN    1
#define SYSCTRL_CFG_SRST_REQ_SVFD0_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_SVFD1_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_SVFD1_OFFSET 1
#define SYSCTRL_CFG_SRST_DREQ_SVFD0_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_SVFD0_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_BISR_S_LEN    1
#define SYSCTRL_CFG_SRST_REQ_BISR_S_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_BISR_S_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_BISR_S_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_PWM_8K_LEN    1
#define SYSCTRL_CFG_SRST_REQ_PWM_8K_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_PWM_8K_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_PWM_8K_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_BISR_LEN    1
#define SYSCTRL_CFG_SRST_REQ_BISR_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_BISR_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_BISR_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_STATUS_LEN    1
#define SYSCTRL_CFG_SRST_REQ_STATUS_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_STATUS_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_STATUS_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_POR_AICORE0_LEN    1
#define SYSCTRL_CFG_SRST_REQ_POR_AICORE0_OFFSET 1
#define SYSCTRL_CFG_SRST_REQ_AICORE0_LEN        1
#define SYSCTRL_CFG_SRST_REQ_AICORE0_OFFSET     0

#define SYSCTRL_CFG_SRST_DREQ_POR_AICORE0_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_POR_AICORE0_OFFSET 1
#define SYSCTRL_CFG_SRST_DREQ_AICORE0_LEN        1
#define SYSCTRL_CFG_SRST_DREQ_AICORE0_OFFSET     0

#define SYSCTRL_CFG_SRST_REQ_POR_AICORE1_LEN    1
#define SYSCTRL_CFG_SRST_REQ_POR_AICORE1_OFFSET 1
#define SYSCTRL_CFG_SRST_REQ_AICORE1_LEN        1
#define SYSCTRL_CFG_SRST_REQ_AICORE1_OFFSET     0

#define SYSCTRL_CFG_SRST_DREQ_POR_AICORE1_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_POR_AICORE1_OFFSET 1
#define SYSCTRL_CFG_SRST_DREQ_AICORE1_LEN        1
#define SYSCTRL_CFG_SRST_DREQ_AICORE1_OFFSET     0

#define SYSCTRL_CFG_SRST_REQ_POR_CPU_LEN    1
#define SYSCTRL_CFG_SRST_REQ_POR_CPU_OFFSET 1
#define SYSCTRL_CFG_SRST_REQ_CPU_LEN        1
#define SYSCTRL_CFG_SRST_REQ_CPU_OFFSET     0

#define SYSCTRL_CFG_SRST_DREQ_POR_CPU_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_POR_CPU_OFFSET 1
#define SYSCTRL_CFG_SRST_DREQ_CPU_LEN        1
#define SYSCTRL_CFG_SRST_DREQ_CPU_OFFSET     0

#define SYSCTRL_CFG_SRST_REQ_SFC_BUS_LEN    1
#define SYSCTRL_CFG_SRST_REQ_SFC_BUS_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_SFC_BUS_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_SFC_BUS_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_TIMESTAMP_LEN    1
#define SYSCTRL_CFG_SRST_REQ_TIMESTAMP_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_TIMESTAMP_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_TIMESTAMP_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_POWER_AICORE0_LEN    1
#define SYSCTRL_CFG_SRST_REQ_POWER_AICORE0_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_POWER_AICORE0_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_POWER_AICORE0_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_POWER_AICORE1_LEN    1
#define SYSCTRL_CFG_SRST_REQ_POWER_AICORE1_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_POWER_AICORE1_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_POWER_AICORE1_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_POWER_CPU_LEN    1
#define SYSCTRL_CFG_SRST_REQ_POWER_CPU_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_POWER_CPU_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_POWER_CPU_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_DJTAG_LEN    1
#define SYSCTRL_CFG_SRST_REQ_DJTAG_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_DJTAG_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_DJTAG_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_FUNC_MBIST_LEN    1
#define SYSCTRL_CFG_SRST_REQ_FUNC_MBIST_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_FUNC_MBIST_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_FUNC_MBIST_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_HPM_LEN    1
#define SYSCTRL_CFG_SRST_REQ_HPM_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_HPM_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_HPM_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_BISR_REPAIR_LEN    1
#define SYSCTRL_CFG_SRST_REQ_BISR_REPAIR_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_BISR_REPAIR_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_BISR_REPAIR_OFFSET 0

#define SYSCTRL_CFG_SRST_REQ_POWER_PCIE_LEN    1
#define SYSCTRL_CFG_SRST_REQ_POWER_PCIE_OFFSET 0

#define SYSCTRL_CFG_SRST_DREQ_POWER_PCIE_LEN    1
#define SYSCTRL_CFG_SRST_DREQ_POWER_PCIE_OFFSET 0

#define SYSCTRL_CFG_SMBUS_SDA_CFG_SET_LEN        1
#define SYSCTRL_CFG_SMBUS_SDA_CFG_SET_OFFSET     11
#define SYSCTRL_CFG_SMBUS_DAT_OE_CFG_SET_LEN     1
#define SYSCTRL_CFG_SMBUS_DAT_OE_CFG_SET_OFFSET  10
#define SYSCTRL_CFG_SMBUS_DAT_MUX_SEL_SET_LEN    1
#define SYSCTRL_CFG_SMBUS_DAT_MUX_SEL_SET_OFFSET 9
#define SYSCTRL_CFG_SMBUS_SCL_CFG_SET_LEN        1
#define SYSCTRL_CFG_SMBUS_SCL_CFG_SET_OFFSET     8
#define SYSCTRL_CFG_SMBUS_CLK_OE_CFG_SET_LEN     1
#define SYSCTRL_CFG_SMBUS_CLK_OE_CFG_SET_OFFSET  7
#define SYSCTRL_CFG_SMBUS_CLK_MUX_SEL_SET_LEN    1
#define SYSCTRL_CFG_SMBUS_CLK_MUX_SEL_SET_OFFSET 6
#define SYSCTRL_CFG_I2C0_SDA_CFG_SET_LEN         1
#define SYSCTRL_CFG_I2C0_SDA_CFG_SET_OFFSET      5
#define SYSCTRL_CFG_I2C0_DAT_OE_CFG_SET_LEN      1
#define SYSCTRL_CFG_I2C0_DAT_OE_CFG_SET_OFFSET   4
#define SYSCTRL_CFG_I2C0_DAT_MUX_SEL_SET_LEN     1
#define SYSCTRL_CFG_I2C0_DAT_MUX_SEL_SET_OFFSET  3
#define SYSCTRL_CFG_I2C0_SCL_CFG_SET_LEN         1
#define SYSCTRL_CFG_I2C0_SCL_CFG_SET_OFFSET      2
#define SYSCTRL_CFG_I2C0_CLK_OE_CFG_SET_LEN      1
#define SYSCTRL_CFG_I2C0_CLK_OE_CFG_SET_OFFSET   1
#define SYSCTRL_CFG_I2C0_CLK_MUX_SEL_SET_LEN     1
#define SYSCTRL_CFG_I2C0_CLK_MUX_SEL_SET_OFFSET  0

#define SYSCTRL_CFG_SMBUS_SDA_CFG_CLR_LEN        1
#define SYSCTRL_CFG_SMBUS_SDA_CFG_CLR_OFFSET     11
#define SYSCTRL_CFG_SMBUS_DAT_OE_CFG_CLR_LEN     1
#define SYSCTRL_CFG_SMBUS_DAT_OE_CFG_CLR_OFFSET  10
#define SYSCTRL_CFG_SMBUS_DAT_MUX_SEL_CLR_LEN    1
#define SYSCTRL_CFG_SMBUS_DAT_MUX_SEL_CLR_OFFSET 9
#define SYSCTRL_CFG_SMBUS_SCL_CFG_CLR_LEN        1
#define SYSCTRL_CFG_SMBUS_SCL_CFG_CLR_OFFSET     8
#define SYSCTRL_CFG_SMBUS_CLK_OE_CFG_CLR_LEN     1
#define SYSCTRL_CFG_SMBUS_CLK_OE_CFG_CLR_OFFSET  7
#define SYSCTRL_CFG_SMBUS_CLK_MUX_SEL_CLR_LEN    1
#define SYSCTRL_CFG_SMBUS_CLK_MUX_SEL_CLR_OFFSET 6
#define SYSCTRL_CFG_I2C0_SDA_CFG_CLR_LEN         1
#define SYSCTRL_CFG_I2C0_SDA_CFG_CLR_OFFSET      5
#define SYSCTRL_CFG_I2C0_DAT_OE_CFG_CLR_LEN      1
#define SYSCTRL_CFG_I2C0_DAT_OE_CFG_CLR_OFFSET   4
#define SYSCTRL_CFG_I2C0_DAT_MUX_SEL_CLR_LEN     1
#define SYSCTRL_CFG_I2C0_DAT_MUX_SEL_CLR_OFFSET  3
#define SYSCTRL_CFG_I2C0_SCL_CFG_CLR_LEN         1
#define SYSCTRL_CFG_I2C0_SCL_CFG_CLR_OFFSET      2
#define SYSCTRL_CFG_I2C0_CLK_OE_CFG_CLR_LEN      1
#define SYSCTRL_CFG_I2C0_CLK_OE_CFG_CLR_OFFSET   1
#define SYSCTRL_CFG_I2C0_CLK_MUX_SEL_CLR_LEN     1
#define SYSCTRL_CFG_I2C0_CLK_MUX_SEL_CLR_OFFSET  0

#define SYSCTRL_CFG_SC_DDR_RETENTION_LEN    1
#define SYSCTRL_CFG_SC_DDR_RETENTION_OFFSET 0

#define SYSCTRL_CFG_SC_WARM_RST_ACK_EN_DDR_LEN    8
#define SYSCTRL_CFG_SC_WARM_RST_ACK_EN_DDR_OFFSET 0

#define SYSCTRL_CFG_ARM_JTAG_SEL_LEN    3
#define SYSCTRL_CFG_ARM_JTAG_SEL_OFFSET 0

#define SYSCTRL_CFG_DBGACK_EN_LEN    1
#define SYSCTRL_CFG_DBGACK_EN_OFFSET 0

#define SYSCTRL_CFG_ERRRSP_DISABLE_LEN    1
#define SYSCTRL_CFG_ERRRSP_DISABLE_OFFSET 0

#define SYSCTRL_CFG_SC_ARUSER_31_0_LEN    32
#define SYSCTRL_CFG_SC_ARUSER_31_0_OFFSET 0

#define SYSCTRL_CFG_SCH_S3_ARUSER_63_32_LEN    32
#define SYSCTRL_CFG_SCH_S3_ARUSER_63_32_OFFSET 0

#define SYSCTRL_CFG_SCH_S3_WUSER_LEN           4
#define SYSCTRL_CFG_SCH_S3_WUSER_OFFSET        12
#define SYSCTRL_CFG_SCH_S3_AWQOS_LEN           4
#define SYSCTRL_CFG_SCH_S3_AWQOS_OFFSET        8
#define SYSCTRL_CFG_SCH_S3_ARQOS_LEN           4
#define SYSCTRL_CFG_SCH_S3_ARQOS_OFFSET        4
#define SYSCTRL_CFG_SCH_S3_ARUSER_67_64_LEN    4
#define SYSCTRL_CFG_SCH_S3_ARUSER_67_64_OFFSET 0

#define SYSCTRL_CFG_SC_AWUSER_31_0_LEN    32
#define SYSCTRL_CFG_SC_AWUSER_31_0_OFFSET 0

#define SYSCTRL_CFG_SCH_S3_AWUSER_63_32_LEN    32
#define SYSCTRL_CFG_SCH_S3_AWUSER_63_32_OFFSET 0

#define SYSCTRL_CFG_SCH_S3_AWUSER_67_64_LEN    4
#define SYSCTRL_CFG_SCH_S3_AWUSER_67_64_OFFSET 0

#define SYSCTRL_CFG_AO_RESET_CTRL_DDR1_LEN    4
#define SYSCTRL_CFG_AO_RESET_CTRL_DDR1_OFFSET 4

#define SYSCTRL_CFG_BYP_MODE_DDRC7_LEN    1
#define SYSCTRL_CFG_BYP_MODE_DDRC7_OFFSET 7
#define SYSCTRL_CFG_BYP_MODE_DDRC6_LEN    1
#define SYSCTRL_CFG_BYP_MODE_DDRC6_OFFSET 6
#define SYSCTRL_CFG_BYP_MODE_DDRC5_LEN    1
#define SYSCTRL_CFG_BYP_MODE_DDRC5_OFFSET 5
#define SYSCTRL_CFG_BYP_MODE_DDRC4_LEN    1
#define SYSCTRL_CFG_BYP_MODE_DDRC4_OFFSET 4

#define SYSCTRL_CFG_TIMER_CLK_SEL_LEN    2
#define SYSCTRL_CFG_TIMER_CLK_SEL_OFFSET 0

#define SYSCTRL_CFG_WDG_CLK_SEL_LEN    2
#define SYSCTRL_CFG_WDG_CLK_SEL_OFFSET 0

#define SYSCTRL_CFG_SFC_CLK_SEL_LEN    2
#define SYSCTRL_CFG_SFC_CLK_SEL_OFFSET 0

#define SYSCTRL_CFG_SC_TIMER_EN_EXTERNAL_LEN    1
#define SYSCTRL_CFG_SC_TIMER_EN_EXTERNAL_OFFSET 0

#define SYSCTRL_CFG_USB3_BUS_FILTER_BYPASS_LEN    4
#define SYSCTRL_CFG_USB3_BUS_FILTER_BYPASS_OFFSET 0

#define SYSCTRL_CFG_USB3_FLADJ_30MHZ_REG_LEN    6
#define SYSCTRL_CFG_USB3_FLADJ_30MHZ_REG_OFFSET 0

#define SYSCTRL_CFG_USB3_REF_CLKDIV2_LEN    1
#define SYSCTRL_CFG_USB3_REF_CLKDIV2_OFFSET 0

#define SYSCTRL_CFG_PME_EN_LEN                        1
#define SYSCTRL_CFG_PME_EN_OFFSET                     19
#define SYSCTRL_CFG_GP_IN_LEN                         16
#define SYSCTRL_CFG_GP_IN_OFFSET                      3
#define SYSCTRL_CFG_SC_USB3_BIGENDIAN_LEN             1
#define SYSCTRL_CFG_SC_USB3_BIGENDIAN_OFFSET          2
#define SYSCTRL_CFG_SC_USB3_UTMIOTG_DMPULLDOWN_LEN    1
#define SYSCTRL_CFG_SC_USB3_UTMIOTG_DMPULLDOWN_OFFSET 1
#define SYSCTRL_CFG_SC_USB3_UTMIOTG_DPPULLDOWN_LEN    1
#define SYSCTRL_CFG_SC_USB3_UTMIOTG_DPPULLDOWN_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_RAM_ECC_EN_LEN    1
#define SYSCTRL_CFG_SC_USB3_RAM_ECC_EN_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_RAM_ECC_CLR_LEN    1
#define SYSCTRL_CFG_SC_USB3_RAM_ECC_CLR_OFFSET 0

#define SYSCTRL_CFG_SC_UTMI_CLK_SEL_LEN    1
#define SYSCTRL_CFG_SC_UTMI_CLK_SEL_OFFSET 0

#define SYSCTRL_CFG_M2_PEWAKE_N_OEN_LEN    1
#define SYSCTRL_CFG_M2_PEWAKE_N_OEN_OFFSET 1
#define SYSCTRL_CFG_M2_CLKREQ_N_OEN_LEN    1
#define SYSCTRL_CFG_M2_CLKREQ_N_OEN_OFFSET 0

#define SYSCTRL_CFG_SC2JA_SELFTEST_ENB_LEN    1
#define SYSCTRL_CFG_SC2JA_SELFTEST_ENB_OFFSET 0

#define SYSCTRL_CFG_HEART_BEAT_NUM_LEN    32
#define SYSCTRL_CFG_HEART_BEAT_NUM_OFFSET 0

#define SYSCTRL_CFG_SC2JA_EMSA_PSS_SEL_LEN    1
#define SYSCTRL_CFG_SC2JA_EMSA_PSS_SEL_OFFSET 0

#define SYSCTRL_CFG_SC_OVERFLOW_CPU_MUX_LEN      1
#define SYSCTRL_CFG_SC_OVERFLOW_CPU_MUX_OFFSET   28
#define SYSCTRL_CFG_SC_CFG_BWC_EN_LEN            1
#define SYSCTRL_CFG_SC_CFG_BWC_EN_OFFSET         27
#define SYSCTRL_CFG_SC_CFG_BWC_SATURATION_LEN    14
#define SYSCTRL_CFG_SC_CFG_BWC_SATURATION_OFFSET 13
#define SYSCTRL_CFG_SC_CFG_BWC_BANDWIDTH_LEN     13
#define SYSCTRL_CFG_SC_CFG_BWC_BANDWIDTH_OFFSET  0

#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_DVPP_LEN            1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_DVPP_OFFSET         20
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_PCIE_LEN            1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_PCIE_OFFSET         19
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_PERI_LLC_HHA_LEN    1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_PERI_LLC_HHA_OFFSET 18
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_PCIE_IO_LEN         1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_PCIE_IO_OFFSET      17
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_DDR0_LEN            1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_DDR0_OFFSET         16
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_DDR1_LEN            1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_DDR1_OFFSET         15
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_CPU_CLUSTER_LEN     1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_CPU_CLUSTER_OFFSET  14
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_TS_LEN              1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_TS_OFFSET           13
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_DVPP_L2BUF_LEN      1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_DVPP_L2BUF_OFFSET   12
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_A55_0_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_A55_0_OFFSET        11
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_A55_1_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_A55_1_OFFSET        10
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_A55_2_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_A55_2_OFFSET        9
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_A55_3_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_A55_3_OFFSET        8
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_A55_4_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_A55_4_OFFSET        7
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_A55_5_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_A55_5_OFFSET        6
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_A55_6_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_A55_6_OFFSET        5
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_A55_7_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_A55_7_OFFSET        4
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_AIC_0_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_AIC_0_OFFSET        3
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_AIC_1_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_AIC_1_OFFSET        2
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_AIC_2_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_AIC_2_OFFSET        1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_AIC_3_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_RSTN_AIC_3_OFFSET        0

#define SYSCTRL_CFG_TIMER_INT_MASK_LEN    1
#define SYSCTRL_CFG_TIMER_INT_MASK_OFFSET 2
#define SYSCTRL_CFG_PCIE_INT_MASK_LEN     1
#define SYSCTRL_CFG_PCIE_INT_MASK_OFFSET  1
#define SYSCTRL_CFG_GPIO_INT_MASK_LEN     1
#define SYSCTRL_CFG_GPIO_INT_MASK_OFFSET  0

#define SYSCTRL_CFG_SC_USB3_PHY_TXRISETUNE0_LEN           2
#define SYSCTRL_CFG_SC_USB3_PHY_TXRISETUNE0_OFFSET        27
#define SYSCTRL_CFG_SC_USB3_PHY_TXRESTUNE0_LEN            2
#define SYSCTRL_CFG_SC_USB3_PHY_TXRESTUNE0_OFFSET         25
#define SYSCTRL_CFG_SC_USB3_PHY_TXPREEMPPULSETUNE0_LEN    1
#define SYSCTRL_CFG_SC_USB3_PHY_TXPREEMPPULSETUNE0_OFFSET 24
#define SYSCTRL_CFG_SC_USB3_PHY_TXPREEMPAMPTUNE0_LEN      2
#define SYSCTRL_CFG_SC_USB3_PHY_TXPREEMPAMPTUNE0_OFFSET   22
#define SYSCTRL_CFG_SC_USB3_PHY_TXHSXVTUNE0_LEN           2
#define SYSCTRL_CFG_SC_USB3_PHY_TXHSXVTUNE0_OFFSET        20
#define SYSCTRL_CFG_SC_USB3_PHY_TXFSLSTUNE0_LEN           4
#define SYSCTRL_CFG_SC_USB3_PHY_TXFSLSTUNE0_OFFSET        16
#define SYSCTRL_CFG_SC_USB3_PHY_SQRXTUNE0_LEN             3
#define SYSCTRL_CFG_SC_USB3_PHY_SQRXTUNE0_OFFSET          13
#define SYSCTRL_CFG_SC_USB3_PHY_REFCLKSEL_LEN             2
#define SYSCTRL_CFG_SC_USB3_PHY_REFCLKSEL_OFFSET          11
#define SYSCTRL_CFG_SC_USB3_PHY_OTGTUNE0_LEN              3
#define SYSCTRL_CFG_SC_USB3_PHY_OTGTUNE0_OFFSET           8
#define SYSCTRL_CFG_SC_USB3_PHY_OTGDISABLE0_LEN           1
#define SYSCTRL_CFG_SC_USB3_PHY_OTGDISABLE0_OFFSET        7
#define SYSCTRL_CFG_SC_USB3_PHY_LOOPBACKENB0_LEN          1
#define SYSCTRL_CFG_SC_USB3_PHY_LOOPBACKENB0_OFFSET       6
#define SYSCTRL_CFG_SC_USB3_PHY_IDPULLUP0_LEN             1
#define SYSCTRL_CFG_SC_USB3_PHY_IDPULLUP0_OFFSET          5
#define SYSCTRL_CFG_SC_USB3_PHY_DRVVBUS0_LEN              1
#define SYSCTRL_CFG_SC_USB3_PHY_DRVVBUS0_OFFSET           4
#define SYSCTRL_CFG_SC_USB3_PHY_COMPDISTUNE0_LEN          3
#define SYSCTRL_CFG_SC_USB3_PHY_COMPDISTUNE0_OFFSET       1
#define SYSCTRL_CFG_SC_USB3_PHY_COMMONONN_LEN             1
#define SYSCTRL_CFG_SC_USB3_PHY_COMMONONN_OFFSET          0

#define SYSCTRL_CFG_SC_USB3_PHY_IDDIG0_LEN                 1
#define SYSCTRL_CFG_SC_USB3_PHY_IDDIG0_OFFSET              24
#define SYSCTRL_CFG_SC_USB3_PHY_FSEL_LEN                   6
#define SYSCTRL_CFG_SC_USB3_PHY_FSEL_OFFSET                18
#define SYSCTRL_CFG_SC_USB3_PHY_TX_VBOOST_LVL_LEN          3
#define SYSCTRL_CFG_SC_USB3_PHY_TX_VBOOST_LVL_OFFSET       15
#define SYSCTRL_CFG_SC_USB3_PHY_TESTE_POWERDOWN_SSP_LEN    1
#define SYSCTRL_CFG_SC_USB3_PHY_TESTE_POWERDOWN_SSP_OFFSET 14
#define SYSCTRL_CFG_SC_USB3_PHY_TESTE_POWERDOWN_HSP_LEN    1
#define SYSCTRL_CFG_SC_USB3_PHY_TESTE_POWERDOWN_HSP_OFFSET 13
#define SYSCTRL_CFG_SC_USB3_PHY_TESTE_BURNIN_LEN           1
#define SYSCTRL_CFG_SC_USB3_PHY_TESTE_BURNIN_OFFSET        12
#define SYSCTRL_CFG_SC_USB3_PHY_REF_USE_PAD_LEN            1
#define SYSCTRL_CFG_SC_USB3_PHY_REF_USE_PAD_OFFSET         11
#define SYSCTRL_CFG_SC_USB3_PHY_REF_SSP_EN_LEN             1
#define SYSCTRL_CFG_SC_USB3_PHY_REF_SSP_EN_OFFSET          10
#define SYSCTRL_CFG_SC_USB3_PHY_VDATSRCENB0_LEN            1
#define SYSCTRL_CFG_SC_USB3_PHY_VDATSRCENB0_OFFSET         9
#define SYSCTRL_CFG_SC_USB3_PHY_VDATDETENB0_LEN            1
#define SYSCTRL_CFG_SC_USB3_PHY_VDATDETENB0_OFFSET         8
#define SYSCTRL_CFG_SC_USB3_PHY_VDATREFTUNE0_LEN           2
#define SYSCTRL_CFG_SC_USB3_PHY_VDATREFTUNE0_OFFSET        6
#define SYSCTRL_CFG_SC_USB3_PHY_VBUSVLDEXTSEL0_LEN         1
#define SYSCTRL_CFG_SC_USB3_PHY_VBUSVLDEXTSEL0_OFFSET      5
#define SYSCTRL_CFG_SC_USB3_PHY_VBUSVLDEXT0_LEN            1
#define SYSCTRL_CFG_SC_USB3_PHY_VBUSVLDEXT0_OFFSET         4
#define SYSCTRL_CFG_SC_USB3_PHY_TXVREFTUNE0_LEN            4
#define SYSCTRL_CFG_SC_USB3_PHY_TXVREFTUNE0_OFFSET         0

#define SYSCTRL_CFG_SC_USB3_PHY_CR_DATA_IN_LEN     16
#define SYSCTRL_CFG_SC_USB3_PHY_CR_DATA_IN_OFFSET  4
#define SYSCTRL_CFG_SC_USB3_PHY_CR_WRITE_LEN       1
#define SYSCTRL_CFG_SC_USB3_PHY_CR_WRITE_OFFSET    3
#define SYSCTRL_CFG_SC_USB3_PHY_CR_READ_LEN        1
#define SYSCTRL_CFG_SC_USB3_PHY_CR_READ_OFFSET     2
#define SYSCTRL_CFG_SC_USB3_PHY_CR_CAP_DAT_LEN     1
#define SYSCTRL_CFG_SC_USB3_PHY_CR_CAP_DAT_OFFSET  1
#define SYSCTRL_CFG_SC_USB3_PHY_CR_CAP_ADDR_LEN    1
#define SYSCTRL_CFG_SC_USB3_PHY_CR_CAP_ADDR_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_PHY_CR_DATA_OUT_LEN    16
#define SYSCTRL_CFG_SC_USB3_PHY_CR_DATA_OUT_OFFSET 1
#define SYSCTRL_CFG_SC_USB3_PHY_CR_ACK_LEN         1
#define SYSCTRL_CFG_SC_USB3_PHY_CR_ACK_OFFSET      0

#define SYSCTRL_CFG_SC_USB3_PHY_LANE0_TX_TERM_OFFSET_LEN    5
#define SYSCTRL_CFG_SC_USB3_PHY_LANE0_TX_TERM_OFFSET_OFFSET 2
#define SYSCTRL_CFG_SC_USB3_PHY_LANE0_TX2RX_LOOPBK_LEN      1
#define SYSCTRL_CFG_SC_USB3_PHY_LANE0_TX2RX_LOOPBK_OFFSET   1
#define SYSCTRL_CFG_SC_USB3_PHY_CLANE0_EXT_PCLK_REQ_LEN     1
#define SYSCTRL_CFG_SC_USB3_PHY_CLANE0_EXT_PCLK_REQ_OFFSET  0

#define SYSCTRL_CFG_SC_USB3_PHY_LOS_LEVEL_LEN    5
#define SYSCTRL_CFG_SC_USB3_PHY_LOS_LEVEL_OFFSET 3
#define SYSCTRL_CFG_SC_USB3_PHY_LOS_BIAS_LEN     3
#define SYSCTRL_CFG_SC_USB3_PHY_LOS_BIAS_OFFSET  0

#define SYSCTRL_CFG_SC_USB3_PHY_MPLL_MULTIPLIER_LEN       7
#define SYSCTRL_CFG_SC_USB3_PHY_MPLL_MULTIPLIER_OFFSET    1
#define SYSCTRL_CFG_SC_USB3_PHY_MPLL_REFSSC_CLK_EN_LEN    1
#define SYSCTRL_CFG_SC_USB3_PHY_MPLL_REFSSC_CLK_EN_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_PHY_PCS_TX_FULL_LEN            7
#define SYSCTRL_CFG_SC_USB3_PHY_PCS_TX_FULL_OFFSET         22
#define SYSCTRL_CFG_SC_USB3_PHY_PCS_TX_DEEMPH_6DB_LEN      6
#define SYSCTRL_CFG_SC_USB3_PHY_PCS_TX_DEEMPH_6DB_OFFSET   16
#define SYSCTRL_CFG_SC_USB3_PHY_PCS_TX_DEEMPH_3P5DB_LEN    6
#define SYSCTRL_CFG_SC_USB3_PHY_PCS_TX_DEEMPH_3P5DB_OFFSET 10
#define SYSCTRL_CFG_SC_USB3_PHY_PCS_RX_LOS_MASK_VAL_LEN    10
#define SYSCTRL_CFG_SC_USB3_PHY_PCS_RX_LOS_MASK_VAL_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_PHY_RTUNE_ACK_LEN    1
#define SYSCTRL_CFG_SC_USB3_PHY_RTUNE_ACK_OFFSET 1
#define SYSCTRL_CFG_SC_USB3_PHY_RTUNE_REQ_LEN    1
#define SYSCTRL_CFG_SC_USB3_PHY_RTUNE_REQ_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_PHY_RX0LOSLFPSEN_LEN       1
#define SYSCTRL_CFG_SC_USB3_PHY_RX0LOSLFPSEN_OFFSET    14
#define SYSCTRL_CFG_SC_USB3_PHY_RETENABLEN_LEN         1
#define SYSCTRL_CFG_SC_USB3_PHY_RETENABLEN_OFFSET      13
#define SYSCTRL_CFG_SC_USB3_PHY_SSC_REF_CLK_SEL_LEN    9
#define SYSCTRL_CFG_SC_USB3_PHY_SSC_REF_CLK_SEL_OFFSET 4
#define SYSCTRL_CFG_SC_USB3_PHY_SSC_RANGE_LEN          3
#define SYSCTRL_CFG_SC_USB3_PHY_SSC_RANGE_OFFSET       1
#define SYSCTRL_CFG_SC_USB3_PHY_SSC_EN_LEN             1
#define SYSCTRL_CFG_SC_USB3_PHY_SSC_EN_OFFSET          0

#define SYSCTRL_CFG_BYPASSDPDATA_LEN    1
#define SYSCTRL_CFG_BYPASSDPDATA_OFFSET 5
#define SYSCTRL_CFG_BYPASSDMDATA_LEN    1
#define SYSCTRL_CFG_BYPASSDMDATA_OFFSET 4
#define SYSCTRL_CFG_BYPASSDPEN_LEN      1
#define SYSCTRL_CFG_BYPASSDPEN_OFFSET   3
#define SYSCTRL_CFG_BYPASSDMEN_LEN      1
#define SYSCTRL_CFG_BYPASSDMEN_OFFSET   2
#define SYSCTRL_CFG_BYPASSSEL_LEN       1
#define SYSCTRL_CFG_BYPASSSEL_OFFSET    1
#define SYSCTRL_CFG_AUTORSMENB_LEN      1
#define SYSCTRL_CFG_AUTORSMENB_OFFSET   0

#define SYSCTRL_CFG_VATESTENB_LEN            1
#define SYSCTRL_CFG_VATESTENB_OFFSET         12
#define SYSCTRL_CFG_ALT_CLK_EN_LEN           1
#define SYSCTRL_CFG_ALT_CLK_EN_OFFSET        10
#define SYSCTRL_CFG_ALT_CLK_SEL_LEN          1
#define SYSCTRL_CFG_ALT_CLK_SEL_OFFSET       9
#define SYSCTRL_CFG_ALT_PCS_CLK_LEN          1
#define SYSCTRL_CFG_ALT_PCS_CLK_OFFSET       8
#define SYSCTRL_CFG_ALT_PIPE_CLK_LEN         1
#define SYSCTRL_CFG_ALT_PIPE_CLK_OFFSET      7
#define SYSCTRL_CFG_REF_REPEAT_CLK_EN_LEN    1
#define SYSCTRL_CFG_REF_REPEAT_CLK_EN_OFFSET 6
#define SYSCTRL_CFG_REF_USE_XO_LEN           1
#define SYSCTRL_CFG_REF_USE_XO_OFFSET        5
#define SYSCTRL_CFG_REF_XO_EN_LEN            1
#define SYSCTRL_CFG_REF_XO_EN_OFFSET         4
#define SYSCTRL_CFG_DCDENB_LEN               1
#define SYSCTRL_CFG_DCDENB_OFFSET            3
#define SYSCTRL_CFG_CHRGSEL_LEN              1
#define SYSCTRL_CFG_CHRGSEL_OFFSET           2
#define SYSCTRL_CFG_CHRGSRCPUENB_LEN         2
#define SYSCTRL_CFG_CHRGSRCPUENB_OFFSET      0

#define SYSCTRL_CFG_TXBITSTUFFEN0_LEN     1
#define SYSCTRL_CFG_TXBITSTUFFEN0_OFFSET  6
#define SYSCTRL_CFG_TXBITSTUFFENH0_LEN    1
#define SYSCTRL_CFG_TXBITSTUFFENH0_OFFSET 5
#define SYSCTRL_CFG_HSXCVREXTCTL_LEN      1
#define SYSCTRL_CFG_HSXCVREXTCTL_OFFSET   4
#define SYSCTRL_CFG_FSDATAEXT_LEN         1
#define SYSCTRL_CFG_FSDATAEXT_OFFSET      3
#define SYSCTRL_CFG_FSSE0EXT_LEN          1
#define SYSCTRL_CFG_FSSE0EXT_OFFSET       2
#define SYSCTRL_CFG_FSXCVROWNER_LEN       1
#define SYSCTRL_CFG_FSXCVROWNER_OFFSET    1
#define SYSCTRL_CFG_TXENABLEN_LEN         1
#define SYSCTRL_CFG_TXENABLEN_OFFSET      0

#define SYSCTRL_CFG_SC_IO_RST_OUT_N_OEN_LEN    1
#define SYSCTRL_CFG_SC_IO_RST_OUT_N_OEN_OFFSET 1
#define SYSCTRL_CFG_SC_PMURST_CTRL_LEN         1
#define SYSCTRL_CFG_SC_PMURST_CTRL_OFFSET      0

#define SYSCTRL_CFG_SC_PCIE_RST_BYPASS_LEN    1
#define SYSCTRL_CFG_SC_PCIE_RST_BYPASS_OFFSET 4
#define SYSCTRL_CFG_SC_DEVRST_CTRL_LEN        1
#define SYSCTRL_CFG_SC_DEVRST_CTRL_OFFSET     3
#define SYSCTRL_CFG_SC_RST_DRAM_CTRL_LEN      2
#define SYSCTRL_CFG_SC_RST_DRAM_CTRL_OFFSET   1
#define SYSCTRL_CFG_SOFT_RST_DRAM_DIS_LEN     1
#define SYSCTRL_CFG_SOFT_RST_DRAM_DIS_OFFSET  0

#define SYSCTRL_CFG_SC_WAIT_DDR_SELFREFLASH_DONEB_YPASS_LEN    1
#define SYSCTRL_CFG_SC_WAIT_DDR_SELFREFLASH_DONEB_YPASS_OFFSET 0

#define SYSCTRL_CFG_SP_RAM_TMOD_SRAM_LEN    7
#define SYSCTRL_CFG_SP_RAM_TMOD_SRAM_OFFSET 0

#define SYSCTRL_CFG_RGMII_ECC_BYPASS_LEN           1
#define SYSCTRL_CFG_RGMII_ECC_BYPASS_OFFSET        27
#define SYSCTRL_CFG_RGMII_TP_RAM_TMOD_LEN          8
#define SYSCTRL_CFG_RGMII_TP_RAM_TMOD_OFFSET       19
#define SYSCTRL_CFG_RGMII_SP_RAM_TMOD_LEN          7
#define SYSCTRL_CFG_RGMII_SP_RAM_TMOD_OFFSET       12
#define SYSCTRL_CFG_RGMII_TP_RAM_POWER_MODE_LEN    6
#define SYSCTRL_CFG_RGMII_TP_RAM_POWER_MODE_OFFSET 6
#define SYSCTRL_CFG_RGMII_SP_RAM_POWER_MODE_LEN    6
#define SYSCTRL_CFG_RGMII_SP_RAM_POWER_MODE_OFFSET 0

#define SYSCTRL_CFG_SMMU_MEM_POWER_MODE_LEN    6
#define SYSCTRL_CFG_SMMU_MEM_POWER_MODE_OFFSET 7
#define SYSCTRL_CFG_SMMU_SP_RAM_TMOD_LEN       7
#define SYSCTRL_CFG_SMMU_SP_RAM_TMOD_OFFSET    0

#define SYSCTRL_CFG_USB_RAM3_ECC_BYPASS_LEN    1
#define SYSCTRL_CFG_USB_RAM3_ECC_BYPASS_OFFSET 27
#define SYSCTRL_CFG_USB_RAM2_ECC_BYPASS_LEN    1
#define SYSCTRL_CFG_USB_RAM2_ECC_BYPASS_OFFSET 26
#define SYSCTRL_CFG_USB_RAM1_ECC_BYPASS_LEN    1
#define SYSCTRL_CFG_USB_RAM1_ECC_BYPASS_OFFSET 25
#define SYSCTRL_CFG_USB_RAM0_ECC_BYPASS_LEN    1
#define SYSCTRL_CFG_USB_RAM0_ECC_BYPASS_OFFSET 24
#define SYSCTRL_CFG_USB_TP_RAM2_TMOD_LEN       8
#define SYSCTRL_CFG_USB_TP_RAM2_TMOD_OFFSET    16
#define SYSCTRL_CFG_USB_TP_RAM1_TMOD_LEN       8
#define SYSCTRL_CFG_USB_TP_RAM1_TMOD_OFFSET    8
#define SYSCTRL_CFG_USB_TP_RAM0_TMOD_LEN       8
#define SYSCTRL_CFG_USB_TP_RAM0_TMOD_OFFSET    0

#define SYSCTRL_CFG_MEM_POWER_MODE_RAM2_USB_LEN    6
#define SYSCTRL_CFG_MEM_POWER_MODE_RAM2_USB_OFFSET 12
#define SYSCTRL_CFG_MEM_POWER_MODE_RAM1_USB_LEN    6
#define SYSCTRL_CFG_MEM_POWER_MODE_RAM1_USB_OFFSET 6
#define SYSCTRL_CFG_MEM_POWER_MODE_RAM0_USB_LEN    6
#define SYSCTRL_CFG_MEM_POWER_MODE_RAM0_USB_OFFSET 0

#define SYSCTRL_CFG_USB_TP_RAM3_TMOD_LEN           8
#define SYSCTRL_CFG_USB_TP_RAM3_TMOD_OFFSET        6
#define SYSCTRL_CFG_MEM_POWER_MODE_RAM3_USB_LEN    6
#define SYSCTRL_CFG_MEM_POWER_MODE_RAM3_USB_OFFSET 0

#define SYSCTRL_CFG_JTAG_AUTH_SP_RAM_TMOD_LEN          7
#define SYSCTRL_CFG_JTAG_AUTH_SP_RAM_TMOD_OFFSET       6
#define SYSCTRL_CFG_JTAG_AUTH_SP_RAM_POWER_MODE_LEN    6
#define SYSCTRL_CFG_JTAG_AUTH_SP_RAM_POWER_MODE_OFFSET 0

#define SYSCTRL_CFG_SC_BOOTROM_TIMING_LEN    32
#define SYSCTRL_CFG_SC_BOOTROM_TIMING_OFFSET 0

#define SYSCTRL_CFG_SC_BYP_EN_SPMI_LEN         1
#define SYSCTRL_CFG_SC_BYP_EN_SPMI_OFFSET      1
#define SYSCTRL_CFG_SC_BYP_EN_RGMII_BUS_LEN    1
#define SYSCTRL_CFG_SC_BYP_EN_RGMII_BUS_OFFSET 0

#define SYSCTRL_CFG_SC_BAK_DATA0_LEN    32
#define SYSCTRL_CFG_SC_BAK_DATA0_OFFSET 0

#define SYSCTRL_CFG_SC_BAK_DATA1_LEN    32
#define SYSCTRL_CFG_SC_BAK_DATA1_OFFSET 0

#define SYSCTRL_CFG_SC_BAK_DATA2_LEN    32
#define SYSCTRL_CFG_SC_BAK_DATA2_OFFSET 0

#define SYSCTRL_CFG_SC_BAK_DATA3_LEN    32
#define SYSCTRL_CFG_SC_BAK_DATA3_OFFSET 0

#define SYSCTRL_CFG_SC_BAK_DATA4_LEN    32
#define SYSCTRL_CFG_SC_BAK_DATA4_OFFSET 0

#define SYSCTRL_CFG_SC_BAK_DATA5_LEN    32
#define SYSCTRL_CFG_SC_BAK_DATA5_OFFSET 0

#define SYSCTRL_CFG_SC_BAK_DATA6_LEN    32
#define SYSCTRL_CFG_SC_BAK_DATA6_OFFSET 0

#define SYSCTRL_CFG_SC_BAK_DATA7_LEN    32
#define SYSCTRL_CFG_SC_BAK_DATA7_OFFSET 0

#define SYSCTRL_CFG_SC_BAK_DATA8_LEN    32
#define SYSCTRL_CFG_SC_BAK_DATA8_OFFSET 0

#define SYSCTRL_CFG_SC_BAK_DATA9_LEN    32
#define SYSCTRL_CFG_SC_BAK_DATA9_OFFSET 0

#define SYSCTRL_CFG_SC_BAK_DATA10_LEN    32
#define SYSCTRL_CFG_SC_BAK_DATA10_OFFSET 0

#define SYSCTRL_CFG_SC_BAK_DATA11_LEN    32
#define SYSCTRL_CFG_SC_BAK_DATA11_OFFSET 0

#define SYSCTRL_CFG_SC_BAK_DATA12_LEN    32
#define SYSCTRL_CFG_SC_BAK_DATA12_OFFSET 0

#define SYSCTRL_CFG_SC_BAK_DATA13_LEN    32
#define SYSCTRL_CFG_SC_BAK_DATA13_OFFSET 0

#define SYSCTRL_CFG_SC_BAK_DATA14_LEN    32
#define SYSCTRL_CFG_SC_BAK_DATA14_OFFSET 0

#define SYSCTRL_CFG_SC_BAK_DATA15_LEN    32
#define SYSCTRL_CFG_SC_BAK_DATA15_OFFSET 0

#define SYSCTRL_CFG_FUNC_MBIST_ENABLE_LEN    1
#define SYSCTRL_CFG_FUNC_MBIST_ENABLE_OFFSET 0

#define SYSCTRL_CFG_FUNC_MBIST_WDATA_LEN    32
#define SYSCTRL_CFG_FUNC_MBIST_WDATA_OFFSET 0

#define SYSCTRL_CFG_FUNC_MBIST_WR_ENABLE_LEN    1
#define SYSCTRL_CFG_FUNC_MBIST_WR_ENABLE_OFFSET 0

#define SYSCTRL_CFG_FUNC_MBIST_RESET_N_LEN    1
#define SYSCTRL_CFG_FUNC_MBIST_RESET_N_OFFSET 0

#define SYSCTRL_CFG_MBIST_REQ_FCM_TS_LEN         1
#define SYSCTRL_CFG_MBIST_REQ_FCM_TS_OFFSET      5
#define SYSCTRL_CFG_MBIST_REQ_AICORE1_LEN        1
#define SYSCTRL_CFG_MBIST_REQ_AICORE1_OFFSET     4
#define SYSCTRL_CFG_MBIST_REQ_AICORE0_LEN        1
#define SYSCTRL_CFG_MBIST_REQ_AICORE0_OFFSET     3
#define SYSCTRL_CFG_MBIST_REQ_L2BUFF1_LEN        1
#define SYSCTRL_CFG_MBIST_REQ_L2BUFF1_OFFSET     2
#define SYSCTRL_CFG_MBIST_REQ_L2BUFF0_LEN        1
#define SYSCTRL_CFG_MBIST_REQ_L2BUFF0_OFFSET     1
#define SYSCTRL_CFG_MBIST_REQ_CPU_CLUSTER_LEN    1
#define SYSCTRL_CFG_MBIST_REQ_CPU_CLUSTER_OFFSET 0

#define SYSCTRL_CFG_RGMII_WADDR_CTRL_LEN    24
#define SYSCTRL_CFG_RGMII_WADDR_CTRL_OFFSET 0

#define SYSCTRL_CFG_RGMII_RADDR_CTRL_LEN    24
#define SYSCTRL_CFG_RGMII_RADDR_CTRL_OFFSET 0

#define SYSCTRL_CFG_SC_CFG_AWUSER_L_RGMII_LEN    32
#define SYSCTRL_CFG_SC_CFG_AWUSER_L_RGMII_OFFSET 0

#define SYSCTRL_CFG_SC_CFG_AWUSER_M_RGMII_LEN    32
#define SYSCTRL_CFG_SC_CFG_AWUSER_M_RGMII_OFFSET 0

#define SYSCTRL_CFG_SC_CFG_AWUSER_H_RGMII_LEN    4
#define SYSCTRL_CFG_SC_CFG_AWUSER_H_RGMII_OFFSET 0

#define SYSCTRL_CFG_SC_CFG_ARUSER_L_RGMII_LEN    32
#define SYSCTRL_CFG_SC_CFG_ARUSER_L_RGMII_OFFSET 0

#define SYSCTRL_CFG_SC_CFG_ARUSER_M_RGMII_LEN    32
#define SYSCTRL_CFG_SC_CFG_ARUSER_M_RGMII_OFFSET 0

#define SYSCTRL_CFG_SC_CFG_ARUSER_H_RGMII_LEN    4
#define SYSCTRL_CFG_SC_CFG_ARUSER_H_RGMII_OFFSET 0

#define SYSCTRL_CFG_SC_CFG_AWQOS_RGMII_LEN    4
#define SYSCTRL_CFG_SC_CFG_AWQOS_RGMII_OFFSET 4
#define SYSCTRL_CFG_SC_CFG_ARQOS_RGMII_LEN    4
#define SYSCTRL_CFG_SC_CFG_ARQOS_RGMII_OFFSET 0

#define SYSCTRL_CFG_SC_CFG_QOS_OVERFLOW_EN_LEN    6
#define SYSCTRL_CFG_SC_CFG_QOS_OVERFLOW_EN_OFFSET 0

#define SYSCTRL_CFG_SC_CFG_QOS_BACKPRESSURE_EN_LEN    3
#define SYSCTRL_CFG_SC_CFG_QOS_BACKPRESSURE_EN_OFFSET 0

#define SYSCTRL_CFG_SC_CFG_QOS_BACKPRESSURE_VALID_LEN    6
#define SYSCTRL_CFG_SC_CFG_QOS_BACKPRESSURE_VALID_OFFSET 0

#define SYSCTRL_CFG_SC_CFG_QOS_EXTEND_CYCLE_NUM_LEN    10
#define SYSCTRL_CFG_SC_CFG_QOS_EXTEND_CYCLE_NUM_OFFSET 0

#define SYSCTRL_CFG_SC_CFG_QOS_VALID_INDICATE_LEN    1
#define SYSCTRL_CFG_SC_CFG_QOS_VALID_INDICATE_OFFSET 0

#define SYSCTRL_CFG_SC_CFG_QOS_OVERFLOW_DDR_LEVEL2_LEN    5
#define SYSCTRL_CFG_SC_CFG_QOS_OVERFLOW_DDR_LEVEL2_OFFSET 5
#define SYSCTRL_CFG_SC_CFG_QOS_OVERFLOW_DDR_LEVEL1_LEN    5
#define SYSCTRL_CFG_SC_CFG_QOS_OVERFLOW_DDR_LEVEL1_OFFSET 0

#define SYSCTRL_CFG_SC_CFG_QOS_BACKPRESSURE_SELECT_LEVEL2_LEN    1
#define SYSCTRL_CFG_SC_CFG_QOS_BACKPRESSURE_SELECT_LEVEL2_OFFSET 1
#define SYSCTRL_CFG_SC_CFG_QOS_BACKPRESSURE_SELECT_LEVEL1_LEN    1
#define SYSCTRL_CFG_SC_CFG_QOS_BACKPRESSURE_SELECT_LEVEL1_OFFSET 0

#define SYSCTRL_CFG_SC_DRAM_RETEION_CLR_LEN    1
#define SYSCTRL_CFG_SC_DRAM_RETEION_CLR_OFFSET 0

#define SYSCTRL_CFG_SC_RST_SRC_CLR_LEN    1
#define SYSCTRL_CFG_SC_RST_SRC_CLR_OFFSET 0

#define SYSCTRL_CFG_AI0_SVFD_DIV64_EN_LEN        1
#define SYSCTRL_CFG_AI0_SVFD_DIV64_EN_OFFSET     9
#define SYSCTRL_CFG_AI0_SVFD_GLITCH_TEST_LEN     1
#define SYSCTRL_CFG_AI0_SVFD_GLITCH_TEST_OFFSET  8
#define SYSCTRL_CFG_AI0_SVFD_MATCH_DETECT_LEN    1
#define SYSCTRL_CFG_AI0_SVFD_MATCH_DETECT_OFFSET 7
#define SYSCTRL_CFG_AI0_SVFD_TRIM_LEN            1
#define SYSCTRL_CFG_AI0_SVFD_TRIM_OFFSET         6
#define SYSCTRL_CFG_AI0_SVFD_ON_MODE_LEN         1
#define SYSCTRL_CFG_AI0_SVFD_ON_MODE_OFFSET      5
#define SYSCTRL_CFG_AI0_SVFD_OFF_MODE_LEN        1
#define SYSCTRL_CFG_AI0_SVFD_OFF_MODE_OFFSET     4
#define SYSCTRL_CFG_AI0_SVFD_D_RATE_LEN          2
#define SYSCTRL_CFG_AI0_SVFD_D_RATE_OFFSET       2
#define SYSCTRL_CFG_AI0_SVFD_VDM_MOD_LEN         2
#define SYSCTRL_CFG_AI0_SVFD_VDM_MOD_OFFSET      0

#define SYSCTRL_CFG_AI0_SVFD_TEST_IN_LEN             4
#define SYSCTRL_CFG_AI0_SVFD_TEST_IN_OFFSET          9
#define SYSCTRL_CFG_AI0_SVFD_CPM_OUT_DIV_SEL_LEN     4
#define SYSCTRL_CFG_AI0_SVFD_CPM_OUT_DIV_SEL_OFFSET  5
#define SYSCTRL_CFG_AI0_SVFD_CPM_DATA_LIMIT_E_LEN    1
#define SYSCTRL_CFG_AI0_SVFD_CPM_DATA_LIMIT_E_OFFSET 4
#define SYSCTRL_CFG_AI0_SVFD_CPM_DATA_MODE_LEN       2
#define SYSCTRL_CFG_AI0_SVFD_CPM_DATA_MODE_OFFSET    2
#define SYSCTRL_CFG_AI0_SVFD_CPM_EDGE_SEL_LEN        1
#define SYSCTRL_CFG_AI0_SVFD_CPM_EDGE_SEL_OFFSET     1
#define SYSCTRL_CFG_AI0_SVFD_CPM_VDM_PERIOD_LEN      1
#define SYSCTRL_CFG_AI0_SVFD_CPM_VDM_PERIOD_OFFSET   0

#define SYSCTRL_CFG_AI0_SVFD_LVT_LL_LEN     4
#define SYSCTRL_CFG_AI0_SVFD_LVT_LL_OFFSET  12
#define SYSCTRL_CFG_AI0_SVFD_LVT_SL_LEN     4
#define SYSCTRL_CFG_AI0_SVFD_LVT_SL_OFFSET  8
#define SYSCTRL_CFG_AI0_SVFD_ULVT_LL_LEN    4
#define SYSCTRL_CFG_AI0_SVFD_ULVT_LL_OFFSET 4
#define SYSCTRL_CFG_AI0_SVFD_ULVT_SL_LEN    4
#define SYSCTRL_CFG_AI0_SVFD_ULVT_SL_OFFSET 0

#define SYSCTRL_CFG_AI1_SVFD_DIV64_EN_LEN        1
#define SYSCTRL_CFG_AI1_SVFD_DIV64_EN_OFFSET     9
#define SYSCTRL_CFG_AI1_SVFD_GLITCH_TEST_LEN     1
#define SYSCTRL_CFG_AI1_SVFD_GLITCH_TEST_OFFSET  8
#define SYSCTRL_CFG_AI1_SVFD_MATCH_DETECT_LEN    1
#define SYSCTRL_CFG_AI1_SVFD_MATCH_DETECT_OFFSET 7
#define SYSCTRL_CFG_AI1_SVFD_TRIM_LEN            1
#define SYSCTRL_CFG_AI1_SVFD_TRIM_OFFSET         6
#define SYSCTRL_CFG_AI1_SVFD_ON_MODE_LEN         1
#define SYSCTRL_CFG_AI1_SVFD_ON_MODE_OFFSET      5
#define SYSCTRL_CFG_AI1_SVFD_OFF_MODE_LEN        1
#define SYSCTRL_CFG_AI1_SVFD_OFF_MODE_OFFSET     4
#define SYSCTRL_CFG_AI1_SVFD_D_RATE_LEN          2
#define SYSCTRL_CFG_AI1_SVFD_D_RATE_OFFSET       2
#define SYSCTRL_CFG_AI1_SVFD_VDM_MOD_LEN         2
#define SYSCTRL_CFG_AI1_SVFD_VDM_MOD_OFFSET      0

#define SYSCTRL_CFG_AI1_SVFD_TEST_IN_LEN             4
#define SYSCTRL_CFG_AI1_SVFD_TEST_IN_OFFSET          9
#define SYSCTRL_CFG_AI1_SVFD_CPM_OUT_DIV_SEL_LEN     4
#define SYSCTRL_CFG_AI1_SVFD_CPM_OUT_DIV_SEL_OFFSET  5
#define SYSCTRL_CFG_AI1_SVFD_CPM_DATA_LIMIT_E_LEN    1
#define SYSCTRL_CFG_AI1_SVFD_CPM_DATA_LIMIT_E_OFFSET 4
#define SYSCTRL_CFG_AI1_SVFD_CPM_DATA_MODE_LEN       2
#define SYSCTRL_CFG_AI1_SVFD_CPM_DATA_MODE_OFFSET    2
#define SYSCTRL_CFG_AI1_SVFD_CPM_EDGE_SEL_LEN        1
#define SYSCTRL_CFG_AI1_SVFD_CPM_EDGE_SEL_OFFSET     1
#define SYSCTRL_CFG_AI1_SVFD_CPM_VDM_PERIOD_LEN      1
#define SYSCTRL_CFG_AI1_SVFD_CPM_VDM_PERIOD_OFFSET   0

#define SYSCTRL_CFG_AI1_SVFD_LVT_LL_LEN     4
#define SYSCTRL_CFG_AI1_SVFD_LVT_LL_OFFSET  12
#define SYSCTRL_CFG_AI1_SVFD_LVT_SL_LEN     4
#define SYSCTRL_CFG_AI1_SVFD_LVT_SL_OFFSET  8
#define SYSCTRL_CFG_AI1_SVFD_ULVT_LL_LEN    4
#define SYSCTRL_CFG_AI1_SVFD_ULVT_LL_OFFSET 4
#define SYSCTRL_CFG_AI1_SVFD_ULVT_SL_LEN    4
#define SYSCTRL_CFG_AI1_SVFD_ULVT_SL_OFFSET 0

#define SYSCTRL_CFG_AI0_SVFD_BYPASS_LEN    1
#define SYSCTRL_CFG_AI0_SVFD_BYPASS_OFFSET 0

#define SYSCTRL_CFG_AI1_SVFD_BYPASS_LEN    1
#define SYSCTRL_CFG_AI1_SVFD_BYPASS_OFFSET 0

#define SYSCTRL_CFG_CPU_IDLE_DIV_BYPASS_LEN      1
#define SYSCTRL_CFG_CPU_IDLE_DIV_BYPASS_OFFSET   31
#define SYSCTRL_CFG_CPU_DIV_CFG_LEN              5
#define SYSCTRL_CFG_CPU_DIV_CFG_OFFSET           26
#define SYSCTRL_CFG_CPU_DIV_IDLE_CFG_LEN         6
#define SYSCTRL_CFG_CPU_DIV_IDLE_CFG_OFFSET      20
#define SYSCTRL_CFG_CPU_AUTO_WAIT_IN_CFG_LEN     10
#define SYSCTRL_CFG_CPU_AUTO_WAIT_IN_CFG_OFFSET  10
#define SYSCTRL_CFG_CPU_AUTO_WAIT_OUT_CFG_LEN    10
#define SYSCTRL_CFG_CPU_AUTO_WAIT_OUT_CFG_OFFSET 0

#define SYSCTRL_CFG_PLL0_CLK_DIV_CFG_EMMC_LEN           4
#define SYSCTRL_CFG_PLL0_CLK_DIV_CFG_EMMC_OFFSET        24
#define SYSCTRL_CFG_PLL0_PROF_CLK_DIV_CFG_AICORE_LEN    6
#define SYSCTRL_CFG_PLL0_PROF_CLK_DIV_CFG_AICORE_OFFSET 18
#define SYSCTRL_CFG_PLL2_PROF_CLK_DIV_CFG_LEN           6
#define SYSCTRL_CFG_PLL2_PROF_CLK_DIV_CFG_OFFSET        12
#define SYSCTRL_CFG_PLL1_PROF_CLK_DIV_CFG_LEN           6
#define SYSCTRL_CFG_PLL1_PROF_CLK_DIV_CFG_OFFSET        6
#define SYSCTRL_CFG_PLL0_PROF_CLK_DIV_CFG_LEN           6
#define SYSCTRL_CFG_PLL0_PROF_CLK_DIV_CFG_OFFSET        0

#define SYSCTRL_CFG_SC_CFG_USBCTRL_SEL_LEN    1
#define SYSCTRL_CFG_SC_CFG_USBCTRL_SEL_OFFSET 0

#define SYSCTRL_CFG_PLL5_PROF_CLK_DIV_CFG_LEN    6
#define SYSCTRL_CFG_PLL5_PROF_CLK_DIV_CFG_OFFSET 12
#define SYSCTRL_CFG_PLL4_PROF_CLK_DIV_CFG_LEN    6
#define SYSCTRL_CFG_PLL4_PROF_CLK_DIV_CFG_OFFSET 6
#define SYSCTRL_CFG_PLL3_PROF_CLK_DIV_CFG_LEN    6
#define SYSCTRL_CFG_PLL3_PROF_CLK_DIV_CFG_OFFSET 0

#define SYSCTRL_CFG_SC_UTMI_WORD_IF_LEN    1
#define SYSCTRL_CFG_SC_UTMI_WORD_IF_OFFSET 0

#define SYSCTRL_CFG_SC_PG_BIAS1_LEN     1
#define SYSCTRL_CFG_SC_PG_BIAS1_OFFSET  3
#define SYSCTRL_CFG_SC_PG_BIAS0_LEN     1
#define SYSCTRL_CFG_SC_PG_BIAS0_OFFSET  2
#define SYSCTRL_CFG_SC_MSC_BIAS1_LEN    1
#define SYSCTRL_CFG_SC_MSC_BIAS1_OFFSET 1
#define SYSCTRL_CFG_SC_MSC_BIAS0_LEN    1
#define SYSCTRL_CFG_SC_MSC_BIAS0_OFFSET 0

#define SYSCTRL_CFG_GMIIRX0_ECC_MULTI_ERR_LEN      1
#define SYSCTRL_CFG_GMIIRX0_ECC_MULTI_ERR_OFFSET   23
#define SYSCTRL_CFG_RDOPT_ECC_MULTI_ERR_LEN        1
#define SYSCTRL_CFG_RDOPT_ECC_MULTI_ERR_OFFSET     22
#define SYSCTRL_CFG_WROPT_ECC_MULTI_ERR_LEN        1
#define SYSCTRL_CFG_WROPT_ECC_MULTI_ERR_OFFSET     21
#define SYSCTRL_CFG_CORETX0_ECC_MULTI_ERR_LEN      1
#define SYSCTRL_CFG_CORETX0_ECC_MULTI_ERR_OFFSET   20
#define SYSCTRL_CFG_CORERX0_ECC_MULTI_ERR_LEN      1
#define SYSCTRL_CFG_CORERX0_ECC_MULTI_ERR_OFFSET   19
#define SYSCTRL_CFG_MACDIO0_ECC_MULTI_ERR_LEN      1
#define SYSCTRL_CFG_MACDIO0_ECC_MULTI_ERR_OFFSET   18
#define SYSCTRL_CFG_PMUTX0_ECC_MULTI_ERR_LEN       1
#define SYSCTRL_CFG_PMUTX0_ECC_MULTI_ERR_OFFSET    17
#define SYSCTRL_CFG_PMURX0_ECC_MULTI_ERR_LEN       1
#define SYSCTRL_CFG_PMURX0_ECC_MULTI_ERR_OFFSET    16
#define SYSCTRL_CFG_PMUDESC03_ECC_MULTI_ERR_LEN    1
#define SYSCTRL_CFG_PMUDESC03_ECC_MULTI_ERR_OFFSET 15
#define SYSCTRL_CFG_PMUDESC02_ECC_MULTI_ERR_LEN    1
#define SYSCTRL_CFG_PMUDESC02_ECC_MULTI_ERR_OFFSET 14
#define SYSCTRL_CFG_PMUDESC01_ECC_MULTI_ERR_LEN    1
#define SYSCTRL_CFG_PMUDESC01_ECC_MULTI_ERR_OFFSET 13
#define SYSCTRL_CFG_PMUDESC00_ECC_MULTI_ERR_LEN    1
#define SYSCTRL_CFG_PMUDESC00_ECC_MULTI_ERR_OFFSET 12
#define SYSCTRL_CFG_GMIIRX0_ECC_ERR_LEN            1
#define SYSCTRL_CFG_GMIIRX0_ECC_ERR_OFFSET         11
#define SYSCTRL_CFG_RDOPT_ECC_ERR_LEN              1
#define SYSCTRL_CFG_RDOPT_ECC_ERR_OFFSET           10
#define SYSCTRL_CFG_WROPT_ECC_ERR_LEN              1
#define SYSCTRL_CFG_WROPT_ECC_ERR_OFFSET           9
#define SYSCTRL_CFG_CORETX0_ECC_ERR_LEN            1
#define SYSCTRL_CFG_CORETX0_ECC_ERR_OFFSET         8
#define SYSCTRL_CFG_CORERX0_ECC_ERR_LEN            1
#define SYSCTRL_CFG_CORERX0_ECC_ERR_OFFSET         7
#define SYSCTRL_CFG_MACDIO0_ECC_ERR_LEN            1
#define SYSCTRL_CFG_MACDIO0_ECC_ERR_OFFSET         6
#define SYSCTRL_CFG_PMUTX0_ECC_ERR_LEN             1
#define SYSCTRL_CFG_PMUTX0_ECC_ERR_OFFSET          5
#define SYSCTRL_CFG_PMURX0_ECC_ERR_LEN             1
#define SYSCTRL_CFG_PMURX0_ECC_ERR_OFFSET          4
#define SYSCTRL_CFG_PMUDESC03_ECC_ERR_LEN          1
#define SYSCTRL_CFG_PMUDESC03_ECC_ERR_OFFSET       3
#define SYSCTRL_CFG_PMUDESC02_ECC_ERR_LEN          1
#define SYSCTRL_CFG_PMUDESC02_ECC_ERR_OFFSET       2
#define SYSCTRL_CFG_PMUDESC01_ECC_ERR_LEN          1
#define SYSCTRL_CFG_PMUDESC01_ECC_ERR_OFFSET       1
#define SYSCTRL_CFG_PMUDESC00_ECC_ERR_LEN          1
#define SYSCTRL_CFG_PMUDESC00_ECC_ERR_OFFSET       0

#define SYSCTRL_CFG_GMIIRX0_ECC_MULTI_ERR_INT_MASK_LEN      1
#define SYSCTRL_CFG_GMIIRX0_ECC_MULTI_ERR_INT_MASK_OFFSET   23
#define SYSCTRL_CFG_RDOPT_ECC_MULTI_ERR_INT_MASK_LEN        1
#define SYSCTRL_CFG_RDOPT_ECC_MULTI_ERR_INT_MASK_OFFSET     22
#define SYSCTRL_CFG_WROPT_ECC_MULTI_ERR_INT_MASK_LEN        1
#define SYSCTRL_CFG_WROPT_ECC_MULTI_ERR_INT_MASK_OFFSET     21
#define SYSCTRL_CFG_CORETX0_ECC_MULTI_ERR_INT_MASK_LEN      1
#define SYSCTRL_CFG_CORETX0_ECC_MULTI_ERR_INT_MASK_OFFSET   20
#define SYSCTRL_CFG_CORERX0_ECC_MULTI_ERR_INT_MASK_LEN      1
#define SYSCTRL_CFG_CORERX0_ECC_MULTI_ERR_INT_MASK_OFFSET   19
#define SYSCTRL_CFG_MACDIO0_ECC_MULTI_ERR_INT_MASK_LEN      1
#define SYSCTRL_CFG_MACDIO0_ECC_MULTI_ERR_INT_MASK_OFFSET   18
#define SYSCTRL_CFG_PMUTX0_ECC_MULTI_ERR_INT_MASK_LEN       1
#define SYSCTRL_CFG_PMUTX0_ECC_MULTI_ERR_INT_MASK_OFFSET    17
#define SYSCTRL_CFG_PMURX0_ECC_MULTI_ERR_INT_MASK_LEN       1
#define SYSCTRL_CFG_PMURX0_ECC_MULTI_ERR_INT_MASK_OFFSET    16
#define SYSCTRL_CFG_PMUDESC03_ECC_MULTI_ERR_INT_MASK_LEN    1
#define SYSCTRL_CFG_PMUDESC03_ECC_MULTI_ERR_INT_MASK_OFFSET 15
#define SYSCTRL_CFG_PMUDESC02_ECC_MULTI_ERR_INT_MASK_LEN    1
#define SYSCTRL_CFG_PMUDESC02_ECC_MULTI_ERR_INT_MASK_OFFSET 14
#define SYSCTRL_CFG_PMUDESC01_ECC_MULTI_ERR_INT_MASK_LEN    1
#define SYSCTRL_CFG_PMUDESC01_ECC_MULTI_ERR_INT_MASK_OFFSET 13
#define SYSCTRL_CFG_PMUDESC00_ECC_MULTI_ERR_INT_MASK_LEN    1
#define SYSCTRL_CFG_PMUDESC00_ECC_MULTI_ERR_INT_MASK_OFFSET 12
#define SYSCTRL_CFG_GMIIRX0_ECC_ERR_INT_MASK_LEN            1
#define SYSCTRL_CFG_GMIIRX0_ECC_ERR_INT_MASK_OFFSET         11
#define SYSCTRL_CFG_RDOPT_ECC_ERR_INT_MASK_LEN              1
#define SYSCTRL_CFG_RDOPT_ECC_ERR_INT_MASK_OFFSET           10
#define SYSCTRL_CFG_WROPT_ECC_ERR_INT_MASK_LEN              1
#define SYSCTRL_CFG_WROPT_ECC_ERR_INT_MASK_OFFSET           9
#define SYSCTRL_CFG_CORETX0_ECC_ERR_INT_MASK_LEN            1
#define SYSCTRL_CFG_CORETX0_ECC_ERR_INT_MASK_OFFSET         8
#define SYSCTRL_CFG_CORERX0_ECC_ERR_INT_MASK_LEN            1
#define SYSCTRL_CFG_CORERX0_ECC_ERR_INT_MASK_OFFSET         7
#define SYSCTRL_CFG_MACDIO0_ECC_ERR_INT_MASK_LEN            1
#define SYSCTRL_CFG_MACDIO0_ECC_ERR_INT_MASK_OFFSET         6
#define SYSCTRL_CFG_PMUTX0_ECC_ERR_INT_MASK_LEN             1
#define SYSCTRL_CFG_PMUTX0_ECC_ERR_INT_MASK_OFFSET          5
#define SYSCTRL_CFG_PMURX0_ECC_ERR_INT_MASK_LEN             1
#define SYSCTRL_CFG_PMURX0_ECC_ERR_INT_MASK_OFFSET          4
#define SYSCTRL_CFG_PMUDESC03_ECC_ERR_INT_MASK_LEN          1
#define SYSCTRL_CFG_PMUDESC03_ECC_ERR_INT_MASK_OFFSET       3
#define SYSCTRL_CFG_PMUDESC02_ECC_ERR_INT_MASK_LEN          1
#define SYSCTRL_CFG_PMUDESC02_ECC_ERR_INT_MASK_OFFSET       2
#define SYSCTRL_CFG_PMUDESC01_ECC_ERR_INT_MASK_LEN          1
#define SYSCTRL_CFG_PMUDESC01_ECC_ERR_INT_MASK_OFFSET       1
#define SYSCTRL_CFG_PMUDESC00_ECC_ERR_INT_MASK_LEN          1
#define SYSCTRL_CFG_PMUDESC00_ECC_ERR_INT_MASK_OFFSET       0

#define SYSCTRL_CFG_SC_WDG_TS_RST_MASK_LEN          1
#define SYSCTRL_CFG_SC_WDG_TS_RST_MASK_OFFSET       19
#define SYSCTRL_CFG_SC_WDG_SECURITY_RST_MASK_LEN    1
#define SYSCTRL_CFG_SC_WDG_SECURITY_RST_MASK_OFFSET 18
#define SYSCTRL_CFG_SC_WDG_RST_MASK_LEN             10
#define SYSCTRL_CFG_SC_WDG_RST_MASK_OFFSET          8
#define SYSCTRL_CFG_SC_WDG_DDR_UCE_RST_MASK_LEN     8
#define SYSCTRL_CFG_SC_WDG_DDR_UCE_RST_MASK_OFFSET  0

#define SYSCTRL_CFG_SC_USB3_TRACE_READ_LEN      1
#define SYSCTRL_CFG_SC_USB3_TRACE_READ_OFFSET   21
#define SYSCTRL_CFG_SC_USB3_TRACE_RADDR_LEN     9
#define SYSCTRL_CFG_SC_USB3_TRACE_RADDR_OFFSET  12
#define SYSCTRL_CFG_SC_USB3_TRACE_POINT_LEN     8
#define SYSCTRL_CFG_SC_USB3_TRACE_POINT_OFFSET  4
#define SYSCTRL_CFG_SC_USB3_TRACE_SEL_LEN       2
#define SYSCTRL_CFG_SC_USB3_TRACE_SEL_OFFSET    2
#define SYSCTRL_CFG_SC_USB3_TRACE_CLEAR_LEN     1
#define SYSCTRL_CFG_SC_USB3_TRACE_CLEAR_OFFSET  1
#define SYSCTRL_CFG_SC_USB3_TRACE_ENABLE_LEN    1
#define SYSCTRL_CFG_SC_USB3_TRACE_ENABLE_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_TRACE_DATA_31_0_LEN    32
#define SYSCTRL_CFG_SC_USB3_TRACE_DATA_31_0_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_TRACE_DATA_63_32_LEN    32
#define SYSCTRL_CFG_SC_USB3_TRACE_DATA_63_32_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_TRACE_DATA_95_64_LEN    32
#define SYSCTRL_CFG_SC_USB3_TRACE_DATA_95_64_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_TRACE_DATA_127_96_LEN    32
#define SYSCTRL_CFG_SC_USB3_TRACE_DATA_127_96_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_TRACE_MASK_31_0_LEN    32
#define SYSCTRL_CFG_SC_USB3_TRACE_MASK_31_0_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_TRACE_MASK_63_32_LEN    32
#define SYSCTRL_CFG_SC_USB3_TRACE_MASK_63_32_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_TRACE_MASK_95_64_LEN    32
#define SYSCTRL_CFG_SC_USB3_TRACE_MASK_95_64_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_TRACE_MASK_127_96_LEN    32
#define SYSCTRL_CFG_SC_USB3_TRACE_MASK_127_96_OFFSET 0

#define SYSCTRL_CFG_TSENSOR_ULTRA_OVER_INT_MASK_AICORE1_LEN    1
#define SYSCTRL_CFG_TSENSOR_ULTRA_OVER_INT_MASK_AICORE1_OFFSET 3
#define SYSCTRL_CFG_TSENSOR_ULTRA_OVER_INT_MASK_AICORE0_LEN    1
#define SYSCTRL_CFG_TSENSOR_ULTRA_OVER_INT_MASK_AICORE0_OFFSET 2
#define SYSCTRL_CFG_TSENSOR_ULTRA_OVER_INT_MASK_TOP_LEN        1
#define SYSCTRL_CFG_TSENSOR_ULTRA_OVER_INT_MASK_TOP_OFFSET     1
#define SYSCTRL_CFG_TSENSOR_ULTRA_OVER_INT_MASK_A55_LEN        1
#define SYSCTRL_CFG_TSENSOR_ULTRA_OVER_INT_MASK_A55_OFFSET     0

#define SYSCTRL_CFG_SC_TS_EN_LEN    1
#define SYSCTRL_CFG_SC_TS_EN_OFFSET 0

#define SYSCTRL_CFG_SC_TIMESTAMP_CLK_SEL_LEN    1
#define SYSCTRL_CFG_SC_TIMESTAMP_CLK_SEL_OFFSET 0

#define SYSCTRL_CFG_SC_SLV_EXT_ACTIVE_LEN    1
#define SYSCTRL_CFG_SC_SLV_EXT_ACTIVE_OFFSET 0

#define SYSCTRL_CFG_SC_RING_LINK_REQ_LEN    1
#define SYSCTRL_CFG_SC_RING_LINK_REQ_OFFSET 0

#define SYSCTRL_CFG_TEMP_ELIM_PERIOD_CFG_LEN     6
#define SYSCTRL_CFG_TEMP_ELIM_PERIOD_CFG_OFFSET  6
#define SYSCTRL_CFG_TEMP_TOTAL_PERIOD_CFG_LEN    6
#define SYSCTRL_CFG_TEMP_TOTAL_PERIOD_CFG_OFFSET 0

#define SYSCTRL_CFG_ARCACHE_USB_LEN    4
#define SYSCTRL_CFG_ARCACHE_USB_OFFSET 4
#define SYSCTRL_CFG_AWCACHE_USB_LEN    4
#define SYSCTRL_CFG_AWCACHE_USB_OFFSET 0

#define SYSCTRL_CFG_ARCACHE_BYPASS_USB_LEN    1
#define SYSCTRL_CFG_ARCACHE_BYPASS_USB_OFFSET 1
#define SYSCTRL_CFG_AWCACHE_BYPASS_USB_LEN    1
#define SYSCTRL_CFG_AWCACHE_BYPASS_USB_OFFSET 0

#define SYSCTRL_CFG_PLL5_UNLOCK_LEN    1
#define SYSCTRL_CFG_PLL5_UNLOCK_OFFSET 5
#define SYSCTRL_CFG_PLL4_UNLOCK_LEN    1
#define SYSCTRL_CFG_PLL4_UNLOCK_OFFSET 4
#define SYSCTRL_CFG_PLL3_UNLOCK_LEN    1
#define SYSCTRL_CFG_PLL3_UNLOCK_OFFSET 3
#define SYSCTRL_CFG_PLL2_UNLOCK_LEN    1
#define SYSCTRL_CFG_PLL2_UNLOCK_OFFSET 2
#define SYSCTRL_CFG_PLL1_UNLOCK_LEN    1
#define SYSCTRL_CFG_PLL1_UNLOCK_OFFSET 1
#define SYSCTRL_CFG_PLL0_UNLOCK_LEN    1
#define SYSCTRL_CFG_PLL0_UNLOCK_OFFSET 0

#define SYSCTRL_CFG_PLL5_UNLOCK_INT_MASK_LEN    1
#define SYSCTRL_CFG_PLL5_UNLOCK_INT_MASK_OFFSET 5
#define SYSCTRL_CFG_PLL4_UNLOCK_INT_MASK_LEN    1
#define SYSCTRL_CFG_PLL4_UNLOCK_INT_MASK_OFFSET 4
#define SYSCTRL_CFG_PLL3_UNLOCK_INT_MASK_LEN    1
#define SYSCTRL_CFG_PLL3_UNLOCK_INT_MASK_OFFSET 3
#define SYSCTRL_CFG_PLL2_UNLOCK_INT_MASK_LEN    1
#define SYSCTRL_CFG_PLL2_UNLOCK_INT_MASK_OFFSET 2
#define SYSCTRL_CFG_PLL1_UNLOCK_INT_MASK_LEN    1
#define SYSCTRL_CFG_PLL1_UNLOCK_INT_MASK_OFFSET 1
#define SYSCTRL_CFG_PLL0_UNLOCK_INT_MASK_LEN    1
#define SYSCTRL_CFG_PLL0_UNLOCK_INT_MASK_OFFSET 0

#define SYSCTRL_CFG_DJTAG_STA_TIMEOUT_LEN    1
#define SYSCTRL_CFG_DJTAG_STA_TIMEOUT_OFFSET 0

#define SYSCTRL_CFG_DJTAG_STA_TIMEOUT_INT_MASK_LEN    1
#define SYSCTRL_CFG_DJTAG_STA_TIMEOUT_INT_MASK_OFFSET 0

#define SYSCTRL_CFG_XTAL_TIME_LEN     16
#define SYSCTRL_CFG_XTAL_TIME_OFFSET  3
#define SYSCTRL_CFG_XTAL_EN_SW_LEN    1
#define SYSCTRL_CFG_XTAL_EN_SW_OFFSET 1
#define SYSCTRL_CFG_XTAL_OVER_LEN     1
#define SYSCTRL_CFG_XTAL_OVER_OFFSET  0

#define SYSCTRL_CFG_SC_ITCR_LEN    1
#define SYSCTRL_CFG_SC_ITCR_OFFSET 0

#define SYSCTRL_CFG_SC_ITIR0_LEN    13
#define SYSCTRL_CFG_SC_ITIR0_OFFSET 0

#define SYSCTRL_CFG_SC_ITOR_LEN    11
#define SYSCTRL_CFG_SC_ITOR_OFFSET 0

#define SYSCTRL_CFG_SC_CNT_DATA_CFG_LEN    25
#define SYSCTRL_CFG_SC_CNT_DATA_CFG_OFFSET 0



#define SYSCTRL_CFG_TEST_LOAD_TIME_LEN    1
#define SYSCTRL_CFG_TEST_LOAD_TIME_OFFSET 2
#define SYSCTRL_CFG_TEST_PLL_EN_LEN       1
#define SYSCTRL_CFG_TEST_PLL_EN_OFFSET    1
#define SYSCTRL_CFG_TEST_MODE_EN_LEN      1
#define SYSCTRL_CFG_TEST_MODE_EN_OFFSET   0

#define SYSCTRL_CFG_IN_MD_TYPE_LEN    1
#define SYSCTRL_CFG_IN_MD_TYPE_OFFSET 7
#define SYSCTRL_CFG_IT_MD_CLK_LEN     3
#define SYSCTRL_CFG_IT_MD_CLK_OFFSET  4
#define SYSCTRL_CFG_IT_MD_CTRL_LEN    3
#define SYSCTRL_CFG_IT_MD_CTRL_OFFSET 1
#define SYSCTRL_CFG_IT_MD_EN_LEN      1
#define SYSCTRL_CFG_IT_MD_EN_OFFSET   0

#define SYSCTRL_CFG_IT_MD_STAT_LEN    1
#define SYSCTRL_CFG_IT_MD_STAT_OFFSET 0

#define SYSCTRL_CFG_PROBE_SYSTEM_COUNTER_VALUE_LEN    16
#define SYSCTRL_CFG_PROBE_SYSTEM_COUNTER_VALUE_OFFSET 0

#define SYSCTRL_CFG_PROBE_SYSTEM_COUNTER_EN_LEN    1
#define SYSCTRL_CFG_PROBE_SYSTEM_COUNTER_EN_OFFSET 0

#define SYSCTRL_CFG_PLL5_LOCK_LEN    1
#define SYSCTRL_CFG_PLL5_LOCK_OFFSET 5
#define SYSCTRL_CFG_PLL4_LOCK_LEN    1
#define SYSCTRL_CFG_PLL4_LOCK_OFFSET 4
#define SYSCTRL_CFG_PLL3_LOCK_LEN    1
#define SYSCTRL_CFG_PLL3_LOCK_OFFSET 3
#define SYSCTRL_CFG_PLL2_LOCK_LEN    1
#define SYSCTRL_CFG_PLL2_LOCK_OFFSET 2
#define SYSCTRL_CFG_PLL1_LOCK_LEN    1
#define SYSCTRL_CFG_PLL1_LOCK_OFFSET 1
#define SYSCTRL_CFG_PLL0_LOCK_LEN    1
#define SYSCTRL_CFG_PLL0_LOCK_OFFSET 0

#define SYSCTRL_CFG_PLL_ON_LEN    1
#define SYSCTRL_CFG_PLL_ON_OFFSET 0

#define SYSCTRL_CFG_WARM_RST_ACKED_LEN    1
#define SYSCTRL_CFG_WARM_RST_ACKED_OFFSET 0

#define SYSCTRL_CFG_RST_STATE_DDR7_LEN    1
#define SYSCTRL_CFG_RST_STATE_DDR7_OFFSET 7
#define SYSCTRL_CFG_RST_STATE_DDR6_LEN    1
#define SYSCTRL_CFG_RST_STATE_DDR6_OFFSET 6
#define SYSCTRL_CFG_RST_STATE_DDR5_LEN    1
#define SYSCTRL_CFG_RST_STATE_DDR5_OFFSET 5
#define SYSCTRL_CFG_RST_STATE_DDR4_LEN    1
#define SYSCTRL_CFG_RST_STATE_DDR4_OFFSET 4

#define SYSCTRL_CFG_ICG_ST_SDMA_LEN    1
#define SYSCTRL_CFG_ICG_ST_SDMA_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_FTE_LEN    1
#define SYSCTRL_CFG_ICG_ST_FTE_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_SMMU_LEN    1
#define SYSCTRL_CFG_ICG_ST_SMMU_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_RGMII_BUS_LEN        1
#define SYSCTRL_CFG_ICG_ST_RGMII_BUS_OFFSET     5
#define SYSCTRL_CFG_ICG_ST_RGMII_GSF_AXI_LEN    1
#define SYSCTRL_CFG_ICG_ST_RGMII_GSF_AXI_OFFSET 4
#define SYSCTRL_CFG_ICG_ST_RGMII_SYS_PUB_LEN    1
#define SYSCTRL_CFG_ICG_ST_RGMII_SYS_PUB_OFFSET 3
#define SYSCTRL_CFG_ICG_ST_RGMII_GSF_125_LEN    1
#define SYSCTRL_CFG_ICG_ST_RGMII_GSF_125_OFFSET 2
#define SYSCTRL_CFG_ICG_ST_RGMII_CRG_125_LEN    1
#define SYSCTRL_CFG_ICG_ST_RGMII_CRG_125_OFFSET 1
#define SYSCTRL_CFG_ICG_ST_RGMII_RX_LEN         1
#define SYSCTRL_CFG_ICG_ST_RGMII_RX_OFFSET      0

#define SYSCTRL_CFG_ICG_ST_USB_BUS_EARLY_LEN    1
#define SYSCTRL_CFG_ICG_ST_USB_BUS_EARLY_OFFSET 3
#define SYSCTRL_CFG_ICG_ST_USB_SUSPEND_LEN      1
#define SYSCTRL_CFG_ICG_ST_USB_SUSPEND_OFFSET   2
#define SYSCTRL_CFG_ICG_ST_USB_PIPE3P_LEN       1
#define SYSCTRL_CFG_ICG_ST_USB_PIPE3P_OFFSET    1
#define SYSCTRL_CFG_ICG_ST_USB_UTMI_LEN         1
#define SYSCTRL_CFG_ICG_ST_USB_UTMI_OFFSET      0

#define SYSCTRL_CFG_ICG_ST_SYS_COUNTER_LEN    1
#define SYSCTRL_CFG_ICG_ST_SYS_COUNTER_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_DDR_LEN    4
#define SYSCTRL_CFG_ICG_ST_DDR_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_HHA1_LEN    1
#define SYSCTRL_CFG_ICG_ST_HHA1_OFFSET 1

#define SYSCTRL_CFG_ICG_ST_MN1_LEN    1
#define SYSCTRL_CFG_ICG_ST_MN1_OFFSET 1

#define SYSCTRL_CFG_ICG_ST_EXMBIST_CFG_LEN     1
#define SYSCTRL_CFG_ICG_ST_EXMBIST_CFG_OFFSET  1
#define SYSCTRL_CFG_ICG_ST_EXMBIST_ACLK_LEN    1
#define SYSCTRL_CFG_ICG_ST_EXMBIST_ACLK_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_DUM_APB_LEN    1
#define SYSCTRL_CFG_ICG_ST_DUM_APB_OFFSET 4
#define SYSCTRL_CFG_ICG_ST_P2P_M_LEN      1
#define SYSCTRL_CFG_ICG_ST_P2P_M_OFFSET   2

#define SYSCTRL_CFG_ICG_ST_PROBE_LEN    1
#define SYSCTRL_CFG_ICG_ST_PROBE_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_LLC_LEN    1
#define SYSCTRL_CFG_ICG_ST_LLC_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_L2BUFF1_LEN    1
#define SYSCTRL_CFG_ICG_ST_L2BUFF1_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_PIPE_LEN            4
#define SYSCTRL_CFG_ICG_ST_PIPE_OFFSET         5
#define SYSCTRL_CFG_ICG_ST_PHY_JTAG_TCK_LEN    1
#define SYSCTRL_CFG_ICG_ST_PHY_JTAG_TCK_OFFSET 4
#define SYSCTRL_CFG_ICG_ST_PHY_CR_PARA_LEN     1
#define SYSCTRL_CFG_ICG_ST_PHY_CR_PARA_OFFSET  3

#define SYSCTRL_CFG_ICG_ST_I2C_LEN    1
#define SYSCTRL_CFG_ICG_ST_I2C_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_TIMER_LEN    1
#define SYSCTRL_CFG_ICG_ST_TIMER_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_GPIO_LEN    2
#define SYSCTRL_CFG_ICG_ST_GPIO_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_SFC_BUS_LEN    1
#define SYSCTRL_CFG_ICG_ST_SFC_BUS_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_REF_LEN    1
#define SYSCTRL_CFG_ICG_ST_REF_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_GPIO_DB_LEN    1
#define SYSCTRL_CFG_ICG_ST_GPIO_DB_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_DJTAG_LEN    1
#define SYSCTRL_CFG_ICG_ST_DJTAG_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_FUNC_MBIST_LEN    1
#define SYSCTRL_CFG_ICG_ST_FUNC_MBIST_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_HPM_LEN    1
#define SYSCTRL_CFG_ICG_ST_HPM_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_ULTRASOC_LEN    1
#define SYSCTRL_CFG_ICG_ST_ULTRASOC_OFFSET 1
#define SYSCTRL_CFG_ICG_ST_CHIE_MON_LEN    1
#define SYSCTRL_CFG_ICG_ST_CHIE_MON_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_SPMI_LEN    1
#define SYSCTRL_CFG_ICG_ST_SPMI_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_PWM_8K_LEN    1
#define SYSCTRL_CFG_ICG_ST_PWM_8K_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_TIMESTAMP_LEN    1
#define SYSCTRL_CFG_ICG_ST_TIMESTAMP_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_MBIST_L2BUFF1_LEN    1
#define SYSCTRL_CFG_ICG_ST_MBIST_L2BUFF1_OFFSET 1
#define SYSCTRL_CFG_ICG_ST_MBIST_L2BUFF0_LEN    1
#define SYSCTRL_CFG_ICG_ST_MBIST_L2BUFF0_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_SRC_AI1_LEN    1
#define SYSCTRL_CFG_ICG_ST_SRC_AI1_OFFSET 1
#define SYSCTRL_CFG_ICG_ST_SRC_AI0_LEN    1
#define SYSCTRL_CFG_ICG_ST_SRC_AI0_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_GIC_CPU_ASYN_LEN    1
#define SYSCTRL_CFG_ICG_ST_GIC_CPU_ASYN_OFFSET 0

#define SYSCTRL_CFG_ICG_ST_CRS_ASYN_LEN    1
#define SYSCTRL_CFG_ICG_ST_CRS_ASYN_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_SDMA_LEN    1
#define SYSCTRL_CFG_SRST_ST_SDMA_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_FTE_LEN    1
#define SYSCTRL_CFG_SRST_ST_FTE_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_USBPHY_PORT_LEN     1
#define SYSCTRL_CFG_SRST_ST_USBPHY_PORT_OFFSET  3
#define SYSCTRL_CFG_SRST_ST_USB_VCC_LEN         1
#define SYSCTRL_CFG_SRST_ST_USB_VCC_OFFSET      2
#define SYSCTRL_CFG_SRST_ST_USBPHY_PIPE0_LEN    1
#define SYSCTRL_CFG_SRST_ST_USBPHY_PIPE0_OFFSET 1
#define SYSCTRL_CFG_SRST_ST_USBPHY_LEN          1
#define SYSCTRL_CFG_SRST_ST_USBPHY_OFFSET       0

#define SYSCTRL_CFG_SRST_ST_RGMII_GSF_LEN       1
#define SYSCTRL_CFG_SRST_ST_RGMII_GSF_OFFSET    1
#define SYSCTRL_CFG_SRST_ST_RGMII_MAC_IF_LEN    1
#define SYSCTRL_CFG_SRST_ST_RGMII_MAC_IF_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_SYS_COUNTER_LEN    1
#define SYSCTRL_CFG_SRST_ST_SYS_COUNTER_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_DDR_LEN    4
#define SYSCTRL_CFG_SRST_ST_DDR_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_HHA1_LEN    1
#define SYSCTRL_CFG_SRST_ST_HHA1_OFFSET 1

#define SYSCTRL_CFG_SRST_ST_MN1_LEN    1
#define SYSCTRL_CFG_SRST_ST_MN1_OFFSET 1

#define SYSCTRL_CFG_SRST_ST_EXMBIST_ARESET_LEN    1
#define SYSCTRL_CFG_SRST_ST_EXMBIST_ARESET_OFFSET 1
#define SYSCTRL_CFG_SRST_ST_EXMBIST_LEN           1
#define SYSCTRL_CFG_SRST_ST_EXMBIST_OFFSET        0

#define SYSCTRL_CFG_SRST_ST_DUM_LEN      1
#define SYSCTRL_CFG_SRST_ST_DUM_OFFSET   4
#define SYSCTRL_CFG_SRST_ST_P2P_M_LEN    1
#define SYSCTRL_CFG_SRST_ST_P2P_M_OFFSET 2

#define SYSCTRL_CFG_SRST_ST_LLC_LEN    1
#define SYSCTRL_CFG_SRST_ST_LLC_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_L2BUFF1_LEN    1
#define SYSCTRL_CFG_SRST_ST_L2BUFF1_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_PCIE_PHY_LEN    1
#define SYSCTRL_CFG_SRST_ST_PCIE_PHY_OFFSET 3
#define SYSCTRL_CFG_SRST_ST_POR_PCIE_LEN    1
#define SYSCTRL_CFG_SRST_ST_POR_PCIE_OFFSET 1
#define SYSCTRL_CFG_SRST_ST_PCIE_LEN        1
#define SYSCTRL_CFG_SRST_ST_PCIE_OFFSET     0

#define SYSCTRL_CFG_SRST_ST_I2C_LEN    1
#define SYSCTRL_CFG_SRST_ST_I2C_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_TIMER_LEN    1
#define SYSCTRL_CFG_SRST_ST_TIMER_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_GPIO_LEN    2
#define SYSCTRL_CFG_SRST_ST_GPIO_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_SPMI_LEN    1
#define SYSCTRL_CFG_SRST_ST_SPMI_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_USB_UTMI_LEN    1
#define SYSCTRL_CFG_SRST_ST_USB_UTMI_OFFSET 0

#define SYSCTRL_CFG_ULTRASOC_SRST_ST_LEN    1
#define SYSCTRL_CFG_ULTRASOC_SRST_ST_OFFSET 1
#define SYSCTRL_CFG_CHIE_MON_SRST_ST_LEN    1
#define SYSCTRL_CFG_CHIE_MON_SRST_ST_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_CPM1_LEN    1
#define SYSCTRL_CFG_SRST_ST_CPM1_OFFSET 1
#define SYSCTRL_CFG_SRST_ST_CPM0_LEN    1
#define SYSCTRL_CFG_SRST_ST_CPM0_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_SVFD1_LEN    1
#define SYSCTRL_CFG_SRST_ST_SVFD1_OFFSET 1
#define SYSCTRL_CFG_SRST_ST_SVFD0_LEN    1
#define SYSCTRL_CFG_SRST_ST_SVFD0_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_BISR_S_LEN    1
#define SYSCTRL_CFG_SRST_ST_BISR_S_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_PWM_8K_LEN    1
#define SYSCTRL_CFG_SRST_ST_PWM_8K_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_BISR_LEN    1
#define SYSCTRL_CFG_SRST_ST_BISR_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_STATUS_LEN    1
#define SYSCTRL_CFG_SRST_ST_STATUS_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_POR_AICORE0_LEN    1
#define SYSCTRL_CFG_SRST_ST_POR_AICORE0_OFFSET 1
#define SYSCTRL_CFG_SRST_ST_AICORE0_LEN        1
#define SYSCTRL_CFG_SRST_ST_AICORE0_OFFSET     0

#define SYSCTRL_CFG_SRST_ST_POR_AICORE1_LEN    1
#define SYSCTRL_CFG_SRST_ST_POR_AICORE1_OFFSET 1
#define SYSCTRL_CFG_SRST_ST_AICORE1_LEN        1
#define SYSCTRL_CFG_SRST_ST_AICORE1_OFFSET     0

#define SYSCTRL_CFG_SRST_ST_POR_CPU_LEN    1
#define SYSCTRL_CFG_SRST_ST_POR_CPU_OFFSET 1
#define SYSCTRL_CFG_SRST_ST_CPU_LEN        1
#define SYSCTRL_CFG_SRST_ST_CPU_OFFSET     0

#define SYSCTRL_CFG_SRST_ST_SFC_BUS_LEN    1
#define SYSCTRL_CFG_SRST_ST_SFC_BUS_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_TIMESTAMP_LEN    1
#define SYSCTRL_CFG_SRST_ST_TIMESTAMP_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_POWER_AICORE0_LEN    1
#define SYSCTRL_CFG_SRST_ST_POWER_AICORE0_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_POWER_AICORE1_LEN    1
#define SYSCTRL_CFG_SRST_ST_POWER_AICORE1_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_POWER_CPU_LEN    1
#define SYSCTRL_CFG_SRST_ST_POWER_CPU_OFFSET 0

#define SYSCTRL_CFG_DJTAG_SRST_ST_LEN    1
#define SYSCTRL_CFG_DJTAG_SRST_ST_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_FUNC_MBIST_LEN    1
#define SYSCTRL_CFG_SRST_ST_FUNC_MBIST_OFFSET 0

#define SYSCTRL_CFG_HPM_SRST_ST_LEN    1
#define SYSCTRL_CFG_HPM_SRST_ST_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_BISR_REPAIR_LEN    1
#define SYSCTRL_CFG_SRST_ST_BISR_REPAIR_OFFSET 0

#define SYSCTRL_CFG_SRST_ST_POWER_PCIE_LEN    1
#define SYSCTRL_CFG_SRST_ST_POWER_PCIE_OFFSET 0

#define SYSCTRL_CFG_SMBUS_SDA_CFG_ST_LEN        1
#define SYSCTRL_CFG_SMBUS_SDA_CFG_ST_OFFSET     11
#define SYSCTRL_CFG_SMBUS_DAT_OE_CFG_ST_LEN     1
#define SYSCTRL_CFG_SMBUS_DAT_OE_CFG_ST_OFFSET  10
#define SYSCTRL_CFG_SMBUS_DAT_MUX_SEL_ST_LEN    1
#define SYSCTRL_CFG_SMBUS_DAT_MUX_SEL_ST_OFFSET 9
#define SYSCTRL_CFG_SMBUS_SCL_CFG_ST_LEN        1
#define SYSCTRL_CFG_SMBUS_SCL_CFG_ST_OFFSET     8
#define SYSCTRL_CFG_SMBUS_CLK_OE_CFG_ST_LEN     1
#define SYSCTRL_CFG_SMBUS_CLK_OE_CFG_ST_OFFSET  7
#define SYSCTRL_CFG_SMBUS_CLK_MUX_SEL_ST_LEN    1
#define SYSCTRL_CFG_SMBUS_CLK_MUX_SEL_ST_OFFSET 6
#define SYSCTRL_CFG_I2C0_SDA_CFG_ST_LEN         1
#define SYSCTRL_CFG_I2C0_SDA_CFG_ST_OFFSET      5
#define SYSCTRL_CFG_I2C0_DAT_OE_CFG_ST_LEN      1
#define SYSCTRL_CFG_I2C0_DAT_OE_CFG_ST_OFFSET   4
#define SYSCTRL_CFG_I2C0_DAT_MUX_SEL_ST_LEN     1
#define SYSCTRL_CFG_I2C0_DAT_MUX_SEL_ST_OFFSET  3
#define SYSCTRL_CFG_I2C0_SCL_CFG_ST_LEN         1
#define SYSCTRL_CFG_I2C0_SCL_CFG_ST_OFFSET      2
#define SYSCTRL_CFG_I2C0_CLK_OE_CFG_ST_LEN      1
#define SYSCTRL_CFG_I2C0_CLK_OE_CFG_ST_OFFSET   1
#define SYSCTRL_CFG_I2C0_CLK_MUX_SEL_ST_LEN     1
#define SYSCTRL_CFG_I2C0_CLK_MUX_SEL_ST_OFFSET  0

#define SYSCTRL_CFG_FLAG_NOW_BCBIST1_LEN    1
#define SYSCTRL_CFG_FLAG_NOW_BCBIST1_OFFSET 3
#define SYSCTRL_CFG_FLAG_BCBIST1_LEN        1
#define SYSCTRL_CFG_FLAG_BCBIST1_OFFSET     2
#define SYSCTRL_CFG_FLAG_NOW_BCBIST0_LEN    1
#define SYSCTRL_CFG_FLAG_NOW_BCBIST0_OFFSET 1
#define SYSCTRL_CFG_FLAG_BCBIST0_LEN        1
#define SYSCTRL_CFG_FLAG_BCBIST0_OFFSET     0

#define SYSCTRL_CFG_JTAG_AUTH_RESULT_L32_LEN    32
#define SYSCTRL_CFG_JTAG_AUTH_RESULT_L32_OFFSET 0

#define SYSCTRL_CFG_JTAG_AUTH_RESULT_H32_LEN    32
#define SYSCTRL_CFG_JTAG_AUTH_RESULT_H32_OFFSET 0

#define SYSCTRL_CFG_AFS3_DFT_DISABLE_LEN       1
#define SYSCTRL_CFG_AFS3_DFT_DISABLE_OFFSET    2
#define SYSCTRL_CFG_AFS3_DJTAG_DISABLE_LEN     1
#define SYSCTRL_CFG_AFS3_DJTAG_DISABLE_OFFSET  1
#define SYSCTRL_CFG_JTAG_AUTH_RESULT_EN_LEN    1
#define SYSCTRL_CFG_JTAG_AUTH_RESULT_EN_OFFSET 0

#define SYSCTRL_CFG_UCE_PROG_STATE_DDRC7_LEN    8
#define SYSCTRL_CFG_UCE_PROG_STATE_DDRC7_OFFSET 24
#define SYSCTRL_CFG_UCE_PROG_STATE_DDRC6_LEN    8
#define SYSCTRL_CFG_UCE_PROG_STATE_DDRC6_OFFSET 16
#define SYSCTRL_CFG_UCE_PROG_STATE_DDRC5_LEN    8
#define SYSCTRL_CFG_UCE_PROG_STATE_DDRC5_OFFSET 8
#define SYSCTRL_CFG_UCE_PROG_STATE_DDRC4_LEN    8
#define SYSCTRL_CFG_UCE_PROG_STATE_DDRC4_OFFSET 0

#define SYSCTRL_CFG_PMUDESC00_MULTI_ERR_ADDR_LEN       5
#define SYSCTRL_CFG_PMUDESC00_MULTI_ERR_ADDR_OFFSET    19
#define SYSCTRL_CFG_PMUDESC00_MULTI_ECC_ERR_SYN_LEN    7
#define SYSCTRL_CFG_PMUDESC00_MULTI_ECC_ERR_SYN_OFFSET 12
#define SYSCTRL_CFG_PMUDESC00_ERR_ADDR_LEN             5
#define SYSCTRL_CFG_PMUDESC00_ERR_ADDR_OFFSET          7
#define SYSCTRL_CFG_PMUDESC00_ECC_ERR_SYN_LEN          7
#define SYSCTRL_CFG_PMUDESC00_ECC_ERR_SYN_OFFSET       0

#define SYSCTRL_CFG_PMUDESC01_MULTI_ERR_ADDR_LEN       5
#define SYSCTRL_CFG_PMUDESC01_MULTI_ERR_ADDR_OFFSET    19
#define SYSCTRL_CFG_PMUDESC01_MULTI_ECC_ERR_SYN_LEN    7
#define SYSCTRL_CFG_PMUDESC01_MULTI_ECC_ERR_SYN_OFFSET 12
#define SYSCTRL_CFG_PMUDESC01_ERR_ADDR_LEN             5
#define SYSCTRL_CFG_PMUDESC01_ERR_ADDR_OFFSET          7
#define SYSCTRL_CFG_PMUDESC01_ECC_ERR_SYN_LEN          7
#define SYSCTRL_CFG_PMUDESC01_ECC_ERR_SYN_OFFSET       0

#define SYSCTRL_CFG_PMUDESC02_MULTI_ERR_ADDR_LEN       5
#define SYSCTRL_CFG_PMUDESC02_MULTI_ERR_ADDR_OFFSET    19
#define SYSCTRL_CFG_PMUDESC02_MULTI_ECC_ERR_SYN_LEN    7
#define SYSCTRL_CFG_PMUDESC02_MULTI_ECC_ERR_SYN_OFFSET 12
#define SYSCTRL_CFG_PMUDESC02_ERR_ADDR_LEN             5
#define SYSCTRL_CFG_PMUDESC02_ERR_ADDR_OFFSET          7
#define SYSCTRL_CFG_PMUDESC02_ECC_ERR_SYN_LEN          7
#define SYSCTRL_CFG_PMUDESC02_ECC_ERR_SYN_OFFSET       0

#define SYSCTRL_CFG_PMUDESC03_MULTI_ERR_ADDR_LEN       5
#define SYSCTRL_CFG_PMUDESC03_MULTI_ERR_ADDR_OFFSET    19
#define SYSCTRL_CFG_PMUDESC03_MULTI_ECC_ERR_SYN_LEN    7
#define SYSCTRL_CFG_PMUDESC03_MULTI_ECC_ERR_SYN_OFFSET 12
#define SYSCTRL_CFG_PMUDESC03_ERR_ADDR_LEN             5
#define SYSCTRL_CFG_PMUDESC03_ERR_ADDR_OFFSET          7
#define SYSCTRL_CFG_PMUDESC03_ECC_ERR_SYN_LEN          7
#define SYSCTRL_CFG_PMUDESC03_ECC_ERR_SYN_OFFSET       0

#define SYSCTRL_CFG_PMURX0_MULTI_ECC_ERR_SYN_LEN    7
#define SYSCTRL_CFG_PMURX0_MULTI_ECC_ERR_SYN_OFFSET 7
#define SYSCTRL_CFG_PMURX0_ECC_ERR_SYN_LEN          7
#define SYSCTRL_CFG_PMURX0_ECC_ERR_SYN_OFFSET       0

#define SYSCTRL_CFG_PMURX0_ERR_ADDR_LEN          10
#define SYSCTRL_CFG_PMURX0_ERR_ADDR_OFFSET       10
#define SYSCTRL_CFG_PMURX0_MULTI_ERR_ADDR_LEN    10
#define SYSCTRL_CFG_PMURX0_MULTI_ERR_ADDR_OFFSET 0

#define SYSCTRL_CFG_PMUTX0_MULTI_ECC_ERR_SYN_LEN    7
#define SYSCTRL_CFG_PMUTX0_MULTI_ECC_ERR_SYN_OFFSET 7
#define SYSCTRL_CFG_PMUTX0_ECC_ERR_SYN_LEN          7
#define SYSCTRL_CFG_PMUTX0_ECC_ERR_SYN_OFFSET       0

#define SYSCTRL_CFG_PMUTX0_ERR_ADDR_LEN          10
#define SYSCTRL_CFG_PMUTX0_ERR_ADDR_OFFSET       10
#define SYSCTRL_CFG_PMUTX0_MULTI_ERR_ADDR_LEN    10
#define SYSCTRL_CFG_PMUTX0_MULTI_ERR_ADDR_OFFSET 0

#define SYSCTRL_CFG_MACDIO0_MULTI_ERR_ADDR_LEN       6
#define SYSCTRL_CFG_MACDIO0_MULTI_ERR_ADDR_OFFSET    20
#define SYSCTRL_CFG_MACDIO0_MULTI_ECC_ERR_SYN_LEN    7
#define SYSCTRL_CFG_MACDIO0_MULTI_ECC_ERR_SYN_OFFSET 13
#define SYSCTRL_CFG_MACDIO0_ERR_ADDR_LEN             6
#define SYSCTRL_CFG_MACDIO0_ERR_ADDR_OFFSET          7
#define SYSCTRL_CFG_MACDIO0_ECC_ERR_SYN_LEN          7
#define SYSCTRL_CFG_MACDIO0_ECC_ERR_SYN_OFFSET       0

#define SYSCTRL_CFG_CORERX0_MULTI_ERR_ADDR_LEN       5
#define SYSCTRL_CFG_CORERX0_MULTI_ERR_ADDR_OFFSET    19
#define SYSCTRL_CFG_CORERX0_MULTI_ECC_ERR_SYN_LEN    7
#define SYSCTRL_CFG_CORERX0_MULTI_ECC_ERR_SYN_OFFSET 12
#define SYSCTRL_CFG_CORERX0_ERR_ADDR_LEN             5
#define SYSCTRL_CFG_CORERX0_ERR_ADDR_OFFSET          7
#define SYSCTRL_CFG_CORERX0_ECC_ERR_SYN_LEN          7
#define SYSCTRL_CFG_CORERX0_ECC_ERR_SYN_OFFSET       0

#define SYSCTRL_CFG_CORETX0_MULTI_ERR_ADDR_LEN       5
#define SYSCTRL_CFG_CORETX0_MULTI_ERR_ADDR_OFFSET    19
#define SYSCTRL_CFG_CORETX0_MULTI_ECC_ERR_SYN_LEN    7
#define SYSCTRL_CFG_CORETX0_MULTI_ECC_ERR_SYN_OFFSET 12
#define SYSCTRL_CFG_CORETX0_ERR_ADDR_LEN             5
#define SYSCTRL_CFG_CORETX0_ERR_ADDR_OFFSET          7
#define SYSCTRL_CFG_CORETX0_ECC_ERR_SYN_LEN          7
#define SYSCTRL_CFG_CORETX0_ECC_ERR_SYN_OFFSET       0

#define SYSCTRL_CFG_WROPT_MULTI_ERR_ADDR_LEN       4
#define SYSCTRL_CFG_WROPT_MULTI_ERR_ADDR_OFFSET    20
#define SYSCTRL_CFG_WROPT_MULTI_ECC_ERR_SYN_LEN    8
#define SYSCTRL_CFG_WROPT_MULTI_ECC_ERR_SYN_OFFSET 12
#define SYSCTRL_CFG_WROPT_ERR_ADDR_LEN             4
#define SYSCTRL_CFG_WROPT_ERR_ADDR_OFFSET          8
#define SYSCTRL_CFG_WROPT_ECC_ERR_SYN_LEN          8
#define SYSCTRL_CFG_WROPT_ECC_ERR_SYN_OFFSET       0

#define SYSCTRL_CFG_RDOPT_MULTI_ERR_ADDR_LEN       5
#define SYSCTRL_CFG_RDOPT_MULTI_ERR_ADDR_OFFSET    21
#define SYSCTRL_CFG_RDOPT_MULTI_ECC_ERR_SYN_LEN    8
#define SYSCTRL_CFG_RDOPT_MULTI_ECC_ERR_SYN_OFFSET 13
#define SYSCTRL_CFG_RDOPT_ERR_ADDR_LEN             5
#define SYSCTRL_CFG_RDOPT_ERR_ADDR_OFFSET          8
#define SYSCTRL_CFG_RDOPT_ECC_ERR_SYN_LEN          8
#define SYSCTRL_CFG_RDOPT_ECC_ERR_SYN_OFFSET       0

#define SYSCTRL_CFG_GMIIRX0_MULTI_ERR_ADDR_LEN       7
#define SYSCTRL_CFG_GMIIRX0_MULTI_ERR_ADDR_OFFSET    19
#define SYSCTRL_CFG_GMIIRX0_MULTI_ECC_ERR_SYN_LEN    6
#define SYSCTRL_CFG_GMIIRX0_MULTI_ECC_ERR_SYN_OFFSET 13
#define SYSCTRL_CFG_GMIIRX0_ERR_ADDR_LEN             7
#define SYSCTRL_CFG_GMIIRX0_ERR_ADDR_OFFSET          6
#define SYSCTRL_CFG_GMIIRX0_ECC_ERR_SYN_LEN          6
#define SYSCTRL_CFG_GMIIRX0_ECC_ERR_SYN_OFFSET       0

#define SYSCTRL_CFG_USB_RAM0_ECC_ERR_ADDR_LEN     11
#define SYSCTRL_CFG_USB_RAM0_ECC_ERR_ADDR_OFFSET  11
#define SYSCTRL_CFG_USB_RAM0_ECC_ERR_SYN_LEN      9
#define SYSCTRL_CFG_USB_RAM0_ECC_ERR_SYN_OFFSET   2
#define SYSCTRL_CFG_USB_RAM0_ECC_ERR_LEN          1
#define SYSCTRL_CFG_USB_RAM0_ECC_ERR_OFFSET       1
#define SYSCTRL_CFG_USB_RAM0_ECC_MULTI_ERR_LEN    1
#define SYSCTRL_CFG_USB_RAM0_ECC_MULTI_ERR_OFFSET 0

#define SYSCTRL_CFG_USB_RAM1_ECC_ERR_ADDR_LEN     13
#define SYSCTRL_CFG_USB_RAM1_ECC_ERR_ADDR_OFFSET  11
#define SYSCTRL_CFG_USB_RAM1_ECC_ERR_SYN_LEN      9
#define SYSCTRL_CFG_USB_RAM1_ECC_ERR_SYN_OFFSET   2
#define SYSCTRL_CFG_USB_RAM1_ECC_ERR_LEN          1
#define SYSCTRL_CFG_USB_RAM1_ECC_ERR_OFFSET       1
#define SYSCTRL_CFG_USB_RAM1_ECC_MULTI_ERR_LEN    1
#define SYSCTRL_CFG_USB_RAM1_ECC_MULTI_ERR_OFFSET 0

#define SYSCTRL_CFG_USB_RAM2_ECC_ERR_ADDR_LEN     9
#define SYSCTRL_CFG_USB_RAM2_ECC_ERR_ADDR_OFFSET  11
#define SYSCTRL_CFG_USB_RAM2_ECC_ERR_SYN_LEN      9
#define SYSCTRL_CFG_USB_RAM2_ECC_ERR_SYN_OFFSET   2
#define SYSCTRL_CFG_USB_RAM2_ECC_ERR_LEN          1
#define SYSCTRL_CFG_USB_RAM2_ECC_ERR_OFFSET       1
#define SYSCTRL_CFG_USB_RAM2_ECC_MULTI_ERR_LEN    1
#define SYSCTRL_CFG_USB_RAM2_ECC_MULTI_ERR_OFFSET 0

#define SYSCTRL_CFG_USB_RAM3_ECC_ERR_ADDR_LEN     9
#define SYSCTRL_CFG_USB_RAM3_ECC_ERR_ADDR_OFFSET  11
#define SYSCTRL_CFG_USB_RAM3_ECC_ERR_SYN_LEN      9
#define SYSCTRL_CFG_USB_RAM3_ECC_ERR_SYN_OFFSET   2
#define SYSCTRL_CFG_USB_RAM3_ECC_ERR_LEN          1
#define SYSCTRL_CFG_USB_RAM3_ECC_ERR_OFFSET       1
#define SYSCTRL_CFG_USB_RAM3_ECC_MULTI_ERR_LEN    1
#define SYSCTRL_CFG_USB_RAM3_ECC_MULTI_ERR_OFFSET 0

#define SYSCTRL_CFG_USB3_TRACE_FIRE_ADDR_LEN    8
#define SYSCTRL_CFG_USB3_TRACE_FIRE_ADDR_OFFSET 2
#define SYSCTRL_CFG_USB3_TRACE_FULL_LEN         1
#define SYSCTRL_CFG_USB3_TRACE_FULL_OFFSET      1
#define SYSCTRL_CFG_USB3_TRACE_DONE_LEN         1
#define SYSCTRL_CFG_USB3_TRACE_DONE_OFFSET      0

#define SYSCTRL_CFG_SC_USB3_TRACE_RDATA_31_0_LEN    32
#define SYSCTRL_CFG_SC_USB3_TRACE_RDATA_31_0_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_TRACE_RDATA_63_32_LEN    32
#define SYSCTRL_CFG_SC_USB3_TRACE_RDATA_63_32_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_TRACE_RDATA_95_64_LEN    32
#define SYSCTRL_CFG_SC_USB3_TRACE_RDATA_95_64_OFFSET 0

#define SYSCTRL_CFG_SC_USB3_TRACE_RDATA_127_96_LEN    32
#define SYSCTRL_CFG_SC_USB3_TRACE_RDATA_127_96_OFFSET 0

#define SYSCTRL_CFG_SC_RING_LINK_ACK_IO_LEN    1
#define SYSCTRL_CFG_SC_RING_LINK_ACK_IO_OFFSET 2
#define SYSCTRL_CFG_SC_RING_LINK_REQ_IO_LEN    1
#define SYSCTRL_CFG_SC_RING_LINK_REQ_IO_OFFSET 1
#define SYSCTRL_CFG_SC_RING_LINK_ACK_LEN       1
#define SYSCTRL_CFG_SC_RING_LINK_ACK_OFFSET    0

#define SYSCTRL_CFG_SC_CPU_IDLE_DIV_STAT_LEN    1
#define SYSCTRL_CFG_SC_CPU_IDLE_DIV_STAT_OFFSET 0

#define SYSCTRL_CFG_SC_DRAM_RETENTION_CTRL_ST_LEN    1
#define SYSCTRL_CFG_SC_DRAM_RETENTION_CTRL_ST_OFFSET 0

#define SYSCTRL_CFG_AI0_SVFD_MATCH_RESULT_LEN     1
#define SYSCTRL_CFG_AI0_SVFD_MATCH_RESULT_OFFSET  2
#define SYSCTRL_CFG_AI0_SVFD_GLITCH_RESULT_LEN    1
#define SYSCTRL_CFG_AI0_SVFD_GLITCH_RESULT_OFFSET 1
#define SYSCTRL_CFG_AI0_SVFD_LOCK_LEN             1
#define SYSCTRL_CFG_AI0_SVFD_LOCK_OFFSET          0

#define SYSCTRL_CFG_AI0_SVFD_CPM_TEST_OUT_LEN      4
#define SYSCTRL_CFG_AI0_SVFD_CPM_TEST_OUT_OFFSET   17
#define SYSCTRL_CFG_AI0_SVFD_CPM_DATA_VALID_LEN    1
#define SYSCTRL_CFG_AI0_SVFD_CPM_DATA_VALID_OFFSET 16
#define SYSCTRL_CFG_AI0_SVFD_CPM_DATA_LEN          16
#define SYSCTRL_CFG_AI0_SVFD_CPM_DATA_OFFSET       0

#define SYSCTRL_CFG_AI1_SVFD_MATCH_RESULT_LEN     1
#define SYSCTRL_CFG_AI1_SVFD_MATCH_RESULT_OFFSET  2
#define SYSCTRL_CFG_AI1_SVFD_GLITCH_RESULT_LEN    1
#define SYSCTRL_CFG_AI1_SVFD_GLITCH_RESULT_OFFSET 1
#define SYSCTRL_CFG_AI1_SVFD_LOCK_LEN             1
#define SYSCTRL_CFG_AI1_SVFD_LOCK_OFFSET          0

#define SYSCTRL_CFG_AI1_SVFD_CPM_TEST_OUT_LEN      4
#define SYSCTRL_CFG_AI1_SVFD_CPM_TEST_OUT_OFFSET   17
#define SYSCTRL_CFG_AI1_SVFD_CPM_DATA_VALID_LEN    1
#define SYSCTRL_CFG_AI1_SVFD_CPM_DATA_VALID_OFFSET 16
#define SYSCTRL_CFG_AI1_SVFD_CPM_DATA_LEN          16
#define SYSCTRL_CFG_AI1_SVFD_CPM_DATA_OFFSET       0

#define SYSCTRL_CFG_SC_RST_SRC_LEN    32
#define SYSCTRL_CFG_SC_RST_SRC_OFFSET 0

#define SYSCTRL_CFG_SC_RST_SRC_FLAG_LEN    1
#define SYSCTRL_CFG_SC_RST_SRC_FLAG_OFFSET 0

#define SYSCTRL_CFG_FUNC_MBIST_RDATA_LEN    32
#define SYSCTRL_CFG_FUNC_MBIST_RDATA_OFFSET 0

#define SYSCTRL_CFG_GMIIRX0_ECC_MULTI_ERR_INT_STATUS_LEN      1
#define SYSCTRL_CFG_GMIIRX0_ECC_MULTI_ERR_INT_STATUS_OFFSET   23
#define SYSCTRL_CFG_RDOPT_ECC_MULTI_ERR_INT_STATUS_LEN        1
#define SYSCTRL_CFG_RDOPT_ECC_MULTI_ERR_INT_STATUS_OFFSET     22
#define SYSCTRL_CFG_WROPT_ECC_MULTI_ERR_INT_STATUS_LEN        1
#define SYSCTRL_CFG_WROPT_ECC_MULTI_ERR_INT_STATUS_OFFSET     21
#define SYSCTRL_CFG_CORETX0_ECC_MULTI_ERR_INT_STATUS_LEN      1
#define SYSCTRL_CFG_CORETX0_ECC_MULTI_ERR_INT_STATUS_OFFSET   20
#define SYSCTRL_CFG_CORERX0_ECC_MULTI_ERR_INT_STATUS_LEN      1
#define SYSCTRL_CFG_CORERX0_ECC_MULTI_ERR_INT_STATUS_OFFSET   19
#define SYSCTRL_CFG_MACDIO0_ECC_MULTI_ERR_INT_STATUS_LEN      1
#define SYSCTRL_CFG_MACDIO0_ECC_MULTI_ERR_INT_STATUS_OFFSET   18
#define SYSCTRL_CFG_PMUTX0_ECC_MULTI_ERR_INT_STATUS_LEN       1
#define SYSCTRL_CFG_PMUTX0_ECC_MULTI_ERR_INT_STATUS_OFFSET    17
#define SYSCTRL_CFG_PMURX0_ECC_MULTI_ERR_INT_STATUS_LEN       1
#define SYSCTRL_CFG_PMURX0_ECC_MULTI_ERR_INT_STATUS_OFFSET    16
#define SYSCTRL_CFG_PMUDESC03_ECC_MULTI_ERR_INT_STATUS_LEN    1
#define SYSCTRL_CFG_PMUDESC03_ECC_MULTI_ERR_INT_STATUS_OFFSET 15
#define SYSCTRL_CFG_PMUDESC02_ECC_MULTI_ERR_INT_STATUS_LEN    1
#define SYSCTRL_CFG_PMUDESC02_ECC_MULTI_ERR_INT_STATUS_OFFSET 14
#define SYSCTRL_CFG_PMUDESC01_ECC_MULTI_ERR_INT_STATUS_LEN    1
#define SYSCTRL_CFG_PMUDESC01_ECC_MULTI_ERR_INT_STATUS_OFFSET 13
#define SYSCTRL_CFG_PMUDESC00_ECC_MULTI_ERR_INT_STATUS_LEN    1
#define SYSCTRL_CFG_PMUDESC00_ECC_MULTI_ERR_INT_STATUS_OFFSET 12
#define SYSCTRL_CFG_GMIIRX0_ECC_ERR_INT_STATUS_LEN            1
#define SYSCTRL_CFG_GMIIRX0_ECC_ERR_INT_STATUS_OFFSET         11
#define SYSCTRL_CFG_RDOPT_ECC_ERR_INT_STATUS_LEN              1
#define SYSCTRL_CFG_RDOPT_ECC_ERR_INT_STATUS_OFFSET           10
#define SYSCTRL_CFG_WROPT_ECC_ERR_INT_STATUS_LEN              1
#define SYSCTRL_CFG_WROPT_ECC_ERR_INT_STATUS_OFFSET           9
#define SYSCTRL_CFG_CORETX0_ECC_ERR_INT_STATUS_LEN            1
#define SYSCTRL_CFG_CORETX0_ECC_ERR_INT_STATUS_OFFSET         8
#define SYSCTRL_CFG_CORERX0_ECC_ERR_INT_STATUS_LEN            1
#define SYSCTRL_CFG_CORERX0_ECC_ERR_INT_STATUS_OFFSET         7
#define SYSCTRL_CFG_MACDIO0_ECC_ERR_INT_STATUS_LEN            1
#define SYSCTRL_CFG_MACDIO0_ECC_ERR_INT_STATUS_OFFSET         6
#define SYSCTRL_CFG_PMUTX0_ECC_ERR_INT_STATUS_LEN             1
#define SYSCTRL_CFG_PMUTX0_ECC_ERR_INT_STATUS_OFFSET          5
#define SYSCTRL_CFG_PMURX0_ECC_ERR_INT_STATUS_LEN             1
#define SYSCTRL_CFG_PMURX0_ECC_ERR_INT_STATUS_OFFSET          4
#define SYSCTRL_CFG_PMUDESC03_ECC_ERR_INT_STATUS_LEN          1
#define SYSCTRL_CFG_PMUDESC03_ECC_ERR_INT_STATUS_OFFSET       3
#define SYSCTRL_CFG_PMUDESC02_ECC_ERR_INT_STATUS_LEN          1
#define SYSCTRL_CFG_PMUDESC02_ECC_ERR_INT_STATUS_OFFSET       2
#define SYSCTRL_CFG_PMUDESC01_ECC_ERR_INT_STATUS_LEN          1
#define SYSCTRL_CFG_PMUDESC01_ECC_ERR_INT_STATUS_OFFSET       1
#define SYSCTRL_CFG_PMUDESC00_ECC_ERR_INT_STATUS_LEN          1
#define SYSCTRL_CFG_PMUDESC00_ECC_ERR_INT_STATUS_OFFSET       0

#define SYSCTRL_CFG_PLL5_UNLOCK_INT_STATUS_LEN    1
#define SYSCTRL_CFG_PLL5_UNLOCK_INT_STATUS_OFFSET 5
#define SYSCTRL_CFG_PLL4_UNLOCK_INT_STATUS_LEN    1
#define SYSCTRL_CFG_PLL4_UNLOCK_INT_STATUS_OFFSET 4
#define SYSCTRL_CFG_PLL3_UNLOCK_INT_STATUS_LEN    1
#define SYSCTRL_CFG_PLL3_UNLOCK_INT_STATUS_OFFSET 3
#define SYSCTRL_CFG_PLL2_UNLOCK_INT_STATUS_LEN    1
#define SYSCTRL_CFG_PLL2_UNLOCK_INT_STATUS_OFFSET 2
#define SYSCTRL_CFG_PLL1_UNLOCK_INT_STATUS_LEN    1
#define SYSCTRL_CFG_PLL1_UNLOCK_INT_STATUS_OFFSET 1
#define SYSCTRL_CFG_PLL0_UNLOCK_INT_STATUS_LEN    1
#define SYSCTRL_CFG_PLL0_UNLOCK_INT_STATUS_OFFSET 0

#define SYSCTRL_CFG_DJTAG_TIMEOUT_INT_STATUS_LEN    1
#define SYSCTRL_CFG_DJTAG_TIMEOUT_INT_STATUS_OFFSET 0

#define SYSCTRL_CFG_TSENSOR_OVER_INT_STATUS_LEN     1
#define SYSCTRL_CFG_TSENSOR_OVER_INT_STATUS_OFFSET  1
#define SYSCTRL_CFG_TSENSOR_UNDER_INT_STATUS_LEN    1
#define SYSCTRL_CFG_TSENSOR_UNDER_INT_STATUS_OFFSET 0

#define SYSCTRL_CFG_XTAL_ON_LEN    1
#define SYSCTRL_CFG_XTAL_ON_OFFSET 0

#define SYSCTRL_CFG_XTAL_PLL_TIMEOUT_LEN    1
#define SYSCTRL_CFG_XTAL_PLL_TIMEOUT_OFFSET 0

#define SYSCTRL_CFG_SC_ITIR0_TST_LEN    13
#define SYSCTRL_CFG_SC_ITIR0_TST_OFFSET 0

#define SYSCTRL_CFG_SC_ITOR_TST_LEN    11
#define SYSCTRL_CFG_SC_ITOR_TST_OFFSET 0

#define SYSCTRL_CFG_SC_CNT_DATA_LEN    25
#define SYSCTRL_CFG_SC_CNT_DATA_OFFSET 0

#define SYSCTRL_CFG_DEEPSLEEP_EN_LEN    1
#define SYSCTRL_CFG_DEEPSLEEP_EN_OFFSET 25

#define SYSCTRL_CFG_SYS_MODE_LEN       4
#define SYSCTRL_CFG_SYS_MODE_OFFSET    8
#define SYSCTRL_CFG_SLEEPED_LEN        1
#define SYSCTRL_CFG_SLEEPED_OFFSET     4
#define SYSCTRL_CFG_DEEPSLEEPED_LEN    1
#define SYSCTRL_CFG_DEEPSLEEPED_OFFSET 0

#define SYSCTRL_CFG_TCXODOWN_BYPASS1_LEN      1
#define SYSCTRL_CFG_TCXODOWN_BYPASS1_OFFSET   25
#define SYSCTRL_CFG_TCXODOWN_BYPASS0_LEN      1
#define SYSCTRL_CFG_TCXODOWN_BYPASS0_OFFSET   24
#define SYSCTRL_CFG_TCXOSEQ1_TIME_LEN         5
#define SYSCTRL_CFG_TCXOSEQ1_TIME_OFFSET      19
#define SYSCTRL_CFG_TCXOSEQ0_TIME_LEN         5
#define SYSCTRL_CFG_TCXOSEQ0_TIME_OFFSET      14
#define SYSCTRL_CFG_TCXOSEQ_BYPASS_LEN        1
#define SYSCTRL_CFG_TCXOSEQ_BYPASS_OFFSET     13
#define SYSCTRL_CFG_TIMEOUT_BYPASS1_LEN       1
#define SYSCTRL_CFG_TIMEOUT_BYPASS1_OFFSET    12
#define SYSCTRL_CFG_TIMEOUT_BYPASS0_LEN       1
#define SYSCTRL_CFG_TIMEOUT_BYPASS0_OFFSET    11
#define SYSCTRL_CFG_CTRLSEL0_APB_LEN          1
#define SYSCTRL_CFG_CTRLSEL0_APB_OFFSET       10
#define SYSCTRL_CFG_CTRLEN0_APB_LEN           1
#define SYSCTRL_CFG_CTRLEN0_APB_OFFSET        9
#define SYSCTRL_CFG_CTRLSEL1_APB_LEN          1
#define SYSCTRL_CFG_CTRLSEL1_APB_OFFSET       8
#define SYSCTRL_CFG_CTRLEN1_APB_LEN           1
#define SYSCTRL_CFG_CTRLEN1_APB_OFFSET        7
#define SYSCTRL_CFG_TCXOFAST1_CTRL_LEN        1
#define SYSCTRL_CFG_TCXOFAST1_CTRL_OFFSET     6
#define SYSCTRL_CFG_TCXOFAST0_CTRL_LEN        1
#define SYSCTRL_CFG_TCXOFAST0_CTRL_OFFSET     5
#define SYSCTRL_CFG_DEFAU_TCXO_LEN            1
#define SYSCTRL_CFG_DEFAU_TCXO_OFFSET         4
#define SYSCTRL_CFG_TCXOSOFT_APB_LEN          1
#define SYSCTRL_CFG_TCXOSOFT_APB_OFFSET       3
#define SYSCTRL_CFG_TCXOSEL_APB_LEN           1
#define SYSCTRL_CFG_TCXOSEL_APB_OFFSET        2
#define SYSCTRL_CFG_TCXOHARDCON_BYPASS_LEN    1
#define SYSCTRL_CFG_TCXOHARDCON_BYPASS_OFFSET 1
#define SYSCTRL_CFG_TCXOPRESEL_APB_LEN        1
#define SYSCTRL_CFG_TCXOPRESEL_APB_OFFSET     0

#define SYSCTRL_CFG_TIMEOUTCNT0_APB_LEN    32
#define SYSCTRL_CFG_TIMEOUTCNT0_APB_OFFSET 0

#define SYSCTRL_CFG_TIMEOUTCNT1_APB_LEN    32
#define SYSCTRL_CFG_TIMEOUTCNT1_APB_OFFSET 0

#define SYSCTRL_CFG_TCXOSEQ_FINISH1_LEN    1
#define SYSCTRL_CFG_TCXOSEQ_FINISH1_OFFSET 13
#define SYSCTRL_CFG_TCXOSEQ_FINISH0_LEN    1
#define SYSCTRL_CFG_TCXOSEQ_FINISH0_OFFSET 12
#define SYSCTRL_CFG_ABBBUF_EN1_LEN         1
#define SYSCTRL_CFG_ABBBUF_EN1_OFFSET      11
#define SYSCTRL_CFG_ABBBUF_EN0_LEN         1
#define SYSCTRL_CFG_ABBBUF_EN0_OFFSET      10
#define SYSCTRL_CFG_CLKGT_CTRL1_LEN        1
#define SYSCTRL_CFG_CLKGT_CTRL1_OFFSET     9
#define SYSCTRL_CFG_CLKGT_CTRL0_LEN        1
#define SYSCTRL_CFG_CLKGT_CTRL0_OFFSET     8
#define SYSCTRL_CFG_CLKGT_CTRL_LEN         1
#define SYSCTRL_CFG_CLKGT_CTRL_OFFSET      7
#define SYSCTRL_CFG_SYSCLK_SEL_LEN         1
#define SYSCTRL_CFG_SYSCLK_SEL_OFFSET      6
#define SYSCTRL_CFG_SYSCLK_EN1_LEN         1
#define SYSCTRL_CFG_SYSCLK_EN1_OFFSET      5
#define SYSCTRL_CFG_SYSCLK_EN0_LEN         1
#define SYSCTRL_CFG_SYSCLK_EN0_OFFSET      4
#define SYSCTRL_CFG_TCXO_TIMEOUT1_LEN      1
#define SYSCTRL_CFG_TCXO_TIMEOUT1_OFFSET   3
#define SYSCTRL_CFG_TCXO_TIMEOUT0_LEN      1
#define SYSCTRL_CFG_TCXO_TIMEOUT0_OFFSET   2
#define SYSCTRL_CFG_TCXO1_EN_LEN           1
#define SYSCTRL_CFG_TCXO1_EN_OFFSET        1
#define SYSCTRL_CFG_TCXO0_EN_LEN           1
#define SYSCTRL_CFG_TCXO0_EN_OFFSET        0

#define SYSCTRL_CFG_PW_PERI_PWRDOWNTIME_LEN    25
#define SYSCTRL_CFG_PW_PERI_PWRDOWNTIME_OFFSET 0

#define SYSCTRL_CFG_PW_PERI_PWRUPTIME_LEN    25
#define SYSCTRL_CFG_PW_PERI_PWRUPTIME_OFFSET 0

#define SYSCTRL_CFG_RING_LINK_BYPASS_LEN          1
#define SYSCTRL_CFG_RING_LINK_BYPASS_OFFSET       25
#define SYSCTRL_CFG_RING_ULNK_BYPASS_LEN          1
#define SYSCTRL_CFG_RING_ULNK_BYPASS_OFFSET       24
#define SYSCTRL_CFG_TIMEOUT_OP_DISISO_LEN         1
#define SYSCTRL_CFG_TIMEOUT_OP_DISISO_OFFSET      23
#define SYSCTRL_CFG_TIMEOUT_OP_RSTON2_LEN         1
#define SYSCTRL_CFG_TIMEOUT_OP_RSTON2_OFFSET      22
#define SYSCTRL_CFG_TIMEOUT_OP_DOWNPERI_LEN       1
#define SYSCTRL_CFG_TIMEOUT_OP_DOWNPERI_OFFSET    21
#define SYSCTRL_CFG_TIMEOUT_OP_ENISO_LEN          1
#define SYSCTRL_CFG_TIMEOUT_OP_ENISO_OFFSET       20
#define SYSCTRL_CFG_TIMEOUT_OP_CLKOFF_LEN         1
#define SYSCTRL_CFG_TIMEOUT_OP_CLKOFF_OFFSET      19
#define SYSCTRL_CFG_TIMEOUT_OP_RSTON_LEN          1
#define SYSCTRL_CFG_TIMEOUT_OP_RSTON_OFFSET       18
#define SYSCTRL_CFG_M3IDLE_BYPASS_LEN             1
#define SYSCTRL_CFG_M3IDLE_BYPASS_OFFSET          16
#define SYSCTRL_CFG_SC_IO_RETENTION_BYPASS_LEN    1
#define SYSCTRL_CFG_SC_IO_RETENTION_BYPASS_OFFSET 11
#define SYSCTRL_CFG_SC_RING_GTEN_BYPASS_LEN       1
#define SYSCTRL_CFG_SC_RING_GTEN_BYPASS_OFFSET    10
#define SYSCTRL_CFG_SC_RING_CLOCK_GTEN_LEN        1
#define SYSCTRL_CFG_SC_RING_CLOCK_GTEN_OFFSET     9
#define SYSCTRL_CFG_SC_PERI_IO_RETENTION_LEN      1
#define SYSCTRL_CFG_SC_PERI_IO_RETENTION_OFFSET   8
#define SYSCTRL_CFG_USB_ISO_EN_LEN                1
#define SYSCTRL_CFG_USB_ISO_EN_OFFSET             7
#define SYSCTRL_CFG_PCIE_ISO_EN_LEN               1
#define SYSCTRL_CFG_PCIE_ISO_EN_OFFSET            6
#define SYSCTRL_CFG_AI1_ISO_EN_LEN                1
#define SYSCTRL_CFG_AI1_ISO_EN_OFFSET             5
#define SYSCTRL_CFG_AI0_ISO_EN_LEN                1
#define SYSCTRL_CFG_AI0_ISO_EN_OFFSET             4
#define SYSCTRL_CFG_DVPP_ISO_EN_LEN               1
#define SYSCTRL_CFG_DVPP_ISO_EN_OFFSET            3
#define SYSCTRL_CFG_DDR_ISO_EN_LEN                1
#define SYSCTRL_CFG_DDR_ISO_EN_OFFSET             2
#define SYSCTRL_CFG_CLUSTER_ISO_EN_LEN            1
#define SYSCTRL_CFG_CLUSTER_ISO_EN_OFFSET         0

#define SYSCTRL_CFG_LP_MD_CTRL_LEN    3
#define SYSCTRL_CFG_LP_MD_CTRL_OFFSET 0

#define SYSCTRL_CFG_SC_SLEEPED_LEN    1
#define SYSCTRL_CFG_SC_SLEEPED_OFFSET 0

#define SYSCTRL_CFG_SC_DEEPSLEEPED_LEN    1
#define SYSCTRL_CFG_SC_DEEPSLEEPED_OFFSET 0

#define SYSCTRL_CFG_DJTAG_SEC_ACC_EN_LEN    1
#define SYSCTRL_CFG_DJTAG_SEC_ACC_EN_OFFSET 0

#define SYSCTRL_CFG_DJTAG_MSTR_ADDR_LEN    31
#define SYSCTRL_CFG_DJTAG_MSTR_ADDR_OFFSET 0

#define SYSCTRL_CFG_DJTAG_MSTR_DATA_LEN    32
#define SYSCTRL_CFG_DJTAG_MSTR_DATA_OFFSET 0

#define SYSCTRL_CFG_DJTAG_MSTR_DISABLE_LEN    1
#define SYSCTRL_CFG_DJTAG_MSTR_DISABLE_OFFSET 31
#define SYSCTRL_CFG_DJTAG_NOR_CFG_EN_LEN      1
#define SYSCTRL_CFG_DJTAG_NOR_CFG_EN_OFFSET   30
#define SYSCTRL_CFG_DJTAG_MSTR_WR_LEN         1
#define SYSCTRL_CFG_DJTAG_MSTR_WR_OFFSET      29
#define SYSCTRL_CFG_DEBUG_MODULE_SEL_LEN      8
#define SYSCTRL_CFG_DEBUG_MODULE_SEL_OFFSET   16
#define SYSCTRL_CFG_CHAIN_UNIT_CFG_EN_LEN     16
#define SYSCTRL_CFG_CHAIN_UNIT_CFG_EN_OFFSET  0

#define SYSCTRL_CFG_DJTAG_MSTR_START_EN_LEN    1
#define SYSCTRL_CFG_DJTAG_MSTR_START_EN_OFFSET 0

#define SYSCTRL_CFG_DJTAG_CPUI_PIPE_EN_LEN          1
#define SYSCTRL_CFG_DJTAG_CPUI_PIPE_EN_OFFSET       8
#define SYSCTRL_CFG_DJTAG_MSTR_PIPE_WAIT_NUM_LEN    7
#define SYSCTRL_CFG_DJTAG_MSTR_PIPE_WAIT_NUM_OFFSET 0

#define SYSCTRL_CFG_DJTAG_TMOUT_LEN    32
#define SYSCTRL_CFG_DJTAG_TMOUT_OFFSET 0

#define SYSCTRL_CFG_DJTAG_NS_ALLOW_LEN    1
#define SYSCTRL_CFG_DJTAG_NS_ALLOW_OFFSET 0

#define SYSCTRL_CFG_EFUSE_AI_FREQ_LOCK_AO_LEN      2
#define SYSCTRL_CFG_EFUSE_AI_FREQ_LOCK_AO_OFFSET   29
#define SYSCTRL_CFG_EFUSE_DVPP_VDEC_HALF_AO_LEN    2
#define SYSCTRL_CFG_EFUSE_DVPP_VDEC_HALF_AO_OFFSET 24
#define SYSCTRL_CFG_EFUSE_ALLSCAN_FORBID_AO_LEN    1
#define SYSCTRL_CFG_EFUSE_ALLSCAN_FORBID_AO_OFFSET 20
#define SYSCTRL_CFG_EFUSE_J2DJS_FORBID_AO_LEN      1
#define SYSCTRL_CFG_EFUSE_J2DJS_FORBID_AO_OFFSET   16
#define SYSCTRL_CFG_EFUSE_SJ2TDRE_FORBID_AO_LEN    1
#define SYSCTRL_CFG_EFUSE_SJ2TDRE_FORBID_AO_OFFSET 12
#define SYSCTRL_CFG_EFUSE_DBGEN_AO_LEN             1
#define SYSCTRL_CFG_EFUSE_DBGEN_AO_OFFSET          11
#define SYSCTRL_CFG_EFUSE_NIDEN_AO_LEN             1
#define SYSCTRL_CFG_EFUSE_NIDEN_AO_OFFSET          10
#define SYSCTRL_CFG_EFUSE_SDBG_CTRL_AO_LEN         2
#define SYSCTRL_CFG_EFUSE_SDBG_CTRL_AO_OFFSET      8
#define SYSCTRL_CFG_EFUSE_JTAG_FORBID_AO_LEN       3
#define SYSCTRL_CFG_EFUSE_JTAG_FORBID_AO_OFFSET    4
#define SYSCTRL_CFG_EFUSE_KEY_CFGED_AO_LEN         1
#define SYSCTRL_CFG_EFUSE_KEY_CFGED_AO_OFFSET      0

#define SYSCTRL_CFG_EFUSE_NS_FORBID_AO_LEN    1
#define SYSCTRL_CFG_EFUSE_NS_FORBID_AO_OFFSET 0

#define SYSCTRL_CFG_EFUSE_SYS_ACCESS_LOCK_AO_LEN    4
#define SYSCTRL_CFG_EFUSE_SYS_ACCESS_LOCK_AO_OFFSET 0

#define SYSCTRL_CFG_PAD_SYSCLK_SEL_LEN      1
#define SYSCTRL_CFG_PAD_SYSCLK_SEL_OFFSET   10
#define SYSCTRL_CFG_PAD_BOOT_CFG_LEN        1
#define SYSCTRL_CFG_PAD_BOOT_CFG_OFFSET     9
#define SYSCTRL_CFG_PAD_A55_SPI_MD_LEN      1
#define SYSCTRL_CFG_PAD_A55_SPI_MD_OFFSET   8
#define SYSCTRL_CFG_PAD_I2C_SLV_ADDR_LEN    3
#define SYSCTRL_CFG_PAD_I2C_SLV_ADDR_OFFSET 5
#define SYSCTRL_CFG_PAD_EMMC_SD_SEL_LEN     1
#define SYSCTRL_CFG_PAD_EMMC_SD_SEL_OFFSET  4
#define SYSCTRL_CFG_PCIE_RC_EP_MD_LEN       1
#define SYSCTRL_CFG_PCIE_RC_EP_MD_OFFSET    3
#define SYSCTRL_CFG_BOOT_MD_INFO_LEN        3
#define SYSCTRL_CFG_BOOT_MD_INFO_OFFSET     0

#define SYSCTRL_CFG_PAD_PROBE_MODE_LEN    1
#define SYSCTRL_CFG_PAD_PROBE_MODE_OFFSET 0

#define SYSCTRL_CFG_LAST_RST_STATUS_LEN    20
#define SYSCTRL_CFG_LAST_RST_STATUS_OFFSET 0

#define SYSCTRL_CFG_BOARD_CFG_INFO_LEN    22
#define SYSCTRL_CFG_BOARD_CFG_INFO_OFFSET 0

#define SYSCTRL_CFG_REPAIR_LOAD_DONE_DVPP_LEN            1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_DVPP_OFFSET         23
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_PCIE_LEN            1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_PCIE_OFFSET         22
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_PERI_LLC_HHA_LEN    1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_PERI_LLC_HHA_OFFSET 21
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_PCIE_IO_LEN         1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_PCIE_IO_OFFSET      20
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_DDR0_LEN            1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_DDR0_OFFSET         19
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_DDR1_LEN            1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_DDR1_OFFSET         18
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_CPU_CLUSTER_LEN     1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_CPU_CLUSTER_OFFSET  17
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_TS_LEN              1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_TS_OFFSET           16
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_DVPP_L2BUF_LEN      1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_DVPP_L2BUF_OFFSET   15
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_A55_0_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_A55_0_OFFSET        14
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_A55_1_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_A55_1_OFFSET        13
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_A55_2_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_A55_2_OFFSET        12
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_A55_3_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_A55_3_OFFSET        11
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_A55_4_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_A55_4_OFFSET        10
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_A55_5_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_A55_5_OFFSET        9
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_A55_6_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_A55_6_OFFSET        8
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_A55_7_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_A55_7_OFFSET        7
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_AIC_0_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_AIC_0_OFFSET        6
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_AIC_1_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_AIC_1_OFFSET        5
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_AIC_2_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_AIC_2_OFFSET        4
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_AIC_3_LEN           1
#define SYSCTRL_CFG_REPAIR_LOAD_DONE_AIC_3_OFFSET        3
#define SYSCTRL_CFG_EFUSE_HARD_REPAIR_DONE2_LEN          1
#define SYSCTRL_CFG_EFUSE_HARD_REPAIR_DONE2_OFFSET       2
#define SYSCTRL_CFG_EFUSE_HARD_REPAIR_DONE1_LEN          1
#define SYSCTRL_CFG_EFUSE_HARD_REPAIR_DONE1_OFFSET       1
#define SYSCTRL_CFG_EFUSE_HARD_REPAIR_DONE0_LEN          1
#define SYSCTRL_CFG_EFUSE_HARD_REPAIR_DONE0_OFFSET       0

#define SYSCTRL_CFG_SYSCTRL_CFG_VERSION0_LEN    32
#define SYSCTRL_CFG_SYSCTRL_CFG_VERSION0_OFFSET 0

#define SYSCTRL_CFG_SYSCTRL_CFG_MAGIC_WORD_LEN    32
#define SYSCTRL_CFG_SYSCTRL_CFG_MAGIC_WORD_OFFSET 0

#define SYSCTRL_CFG_SYSCTRL_CFG_ECO_CFG0_LEN    32
#define SYSCTRL_CFG_SYSCTRL_CFG_ECO_CFG0_OFFSET 0

#define SYSCTRL_CFG_SYSCTRL_CFG_ECO_CFG1_LEN    32
#define SYSCTRL_CFG_SYSCTRL_CFG_ECO_CFG1_OFFSET 0

#define SYSCTRL_CFG_SYSCTRL_CFG_ECO_CFG2_LEN    32
#define SYSCTRL_CFG_SYSCTRL_CFG_ECO_CFG2_OFFSET 0

#define SYSCTRL_CFG_SYSCTRL_CFG_ECO_CFG3_LEN    32
#define SYSCTRL_CFG_SYSCTRL_CFG_ECO_CFG3_OFFSET 0

#define SYSCTRL_CFG_DIE_ID31_0_LEN    32
#define SYSCTRL_CFG_DIE_ID31_0_OFFSET 0

#define SYSCTRL_CFG_DIE_ID63_32_LEN    32
#define SYSCTRL_CFG_DIE_ID63_32_OFFSET 0

#define SYSCTRL_CFG_DIE_ID95_64_LEN    32
#define SYSCTRL_CFG_DIE_ID95_64_OFFSET 0

#define SYSCTRL_CFG_DIE_ID127_96_LEN    32
#define SYSCTRL_CFG_DIE_ID127_96_OFFSET 0

#define SYSCTRL_CFG_DIE_ID159_128_LEN    32
#define SYSCTRL_CFG_DIE_ID159_128_OFFSET 0

#define SYSCTRL_CFG_DIE_ID191_160_LEN    32
#define SYSCTRL_CFG_DIE_ID191_160_OFFSET 0

#define SYSCTRL_CFG_DIE_ID223_192_LEN    32
#define SYSCTRL_CFG_DIE_ID223_192_OFFSET 0

#define SYSCTRL_CFG_DIE_ID255_224_LEN    32
#define SYSCTRL_CFG_DIE_ID255_224_OFFSET 0

#define SYSCTRL_CFG_DJTAG_RD_DATA0_LEN    32
#define SYSCTRL_CFG_DJTAG_RD_DATA0_OFFSET 0

#define SYSCTRL_CFG_DJTAG_RD_DATA1_LEN    32
#define SYSCTRL_CFG_DJTAG_RD_DATA1_OFFSET 0

#define SYSCTRL_CFG_DJTAG_RD_DATA2_LEN    32
#define SYSCTRL_CFG_DJTAG_RD_DATA2_OFFSET 0

#define SYSCTRL_CFG_DJTAG_RD_DATA3_LEN    32
#define SYSCTRL_CFG_DJTAG_RD_DATA3_OFFSET 0

#define SYSCTRL_CFG_DJTAG_RD_DATA4_LEN    32
#define SYSCTRL_CFG_DJTAG_RD_DATA4_OFFSET 0

#define SYSCTRL_CFG_DJTAG_RD_DATA5_LEN    32
#define SYSCTRL_CFG_DJTAG_RD_DATA5_OFFSET 0

#define SYSCTRL_CFG_DJTAG_RD_DATA6_LEN    32
#define SYSCTRL_CFG_DJTAG_RD_DATA6_OFFSET 0

#define SYSCTRL_CFG_DJTAG_RD_DATA7_LEN    32
#define SYSCTRL_CFG_DJTAG_RD_DATA7_OFFSET 0

#define SYSCTRL_CFG_DJTAG_RD_DATA8_LEN    32
#define SYSCTRL_CFG_DJTAG_RD_DATA8_OFFSET 0

#define SYSCTRL_CFG_DJTAG_RD_DATA9_LEN    32
#define SYSCTRL_CFG_DJTAG_RD_DATA9_OFFSET 0

#define SYSCTRL_CFG_RDATA_CHANGED_LEN    10
#define SYSCTRL_CFG_RDATA_CHANGED_OFFSET 16
#define SYSCTRL_CFG_DEBUG_BUS_EN_LEN     1
#define SYSCTRL_CFG_DEBUG_BUS_EN_OFFSET  9
#define SYSCTRL_CFG_DJTAG_OP_DONE_LEN    1
#define SYSCTRL_CFG_DJTAG_OP_DONE_OFFSET 8
#define SYSCTRL_CFG_UNIT_CONFLICT_LEN    8
#define SYSCTRL_CFG_UNIT_CONFLICT_OFFSET 0

#define SYSCTRL_CFG_USB3_DEBUG_31_0_LEN    32
#define SYSCTRL_CFG_USB3_DEBUG_31_0_OFFSET 0

#define SYSCTRL_CFG_USB3_DEBUG_63_32_LEN    32
#define SYSCTRL_CFG_USB3_DEBUG_63_32_OFFSET 0

#define SYSCTRL_CFG_USB3_LOGIC_ANALYZER_TRACE_31_0_LEN    32
#define SYSCTRL_CFG_USB3_LOGIC_ANALYZER_TRACE_31_0_OFFSET 0

#define SYSCTRL_CFG_USB3_LOGIC_ANALYZER_TRACE_63_32_LEN    32
#define SYSCTRL_CFG_USB3_LOGIC_ANALYZER_TRACE_63_32_OFFSET 0

#define SYSCTRL_CFG_AVALID0_LEN            1
#define SYSCTRL_CFG_AVALID0_OFFSET         18
#define SYSCTRL_CFG_CHGDET0_LEN            1
#define SYSCTRL_CFG_CHGDET0_OFFSET         17
#define SYSCTRL_CFG_DMSEHV0_LEN            1
#define SYSCTRL_CFG_DMSEHV0_OFFSET         16
#define SYSCTRL_CFG_DPSEHV0_LEN            1
#define SYSCTRL_CFG_DPSEHV0_OFFSET         15
#define SYSCTRL_CFG_FSLSRCV0_LEN           1
#define SYSCTRL_CFG_FSLSRCV0_OFFSET        14
#define SYSCTRL_CFG_FSVMINUS0_LEN          1
#define SYSCTRL_CFG_FSVMINUS0_OFFSET       13
#define SYSCTRL_CFG_FSVPLUS0_LEN           1
#define SYSCTRL_CFG_FSVPLUS0_OFFSET        12
#define SYSCTRL_CFG_HOSTDISCONNECT0_LEN    1
#define SYSCTRL_CFG_HOSTDISCONNECT0_OFFSET 11
#define SYSCTRL_CFG_HSRXDAT0_LEN           1
#define SYSCTRL_CFG_HSRXDAT0_OFFSET        10
#define SYSCTRL_CFG_HSSQUELCH0_LEN         1
#define SYSCTRL_CFG_HSSQUELCH0_OFFSET      9
#define SYSCTRL_CFG_IDHV0_LEN              1
#define SYSCTRL_CFG_IDHV0_OFFSET           8
#define SYSCTRL_CFG_OTGSESSVLD0_LEN        1
#define SYSCTRL_CFG_OTGSESSVLD0_OFFSET     7
#define SYSCTRL_CFG_OTGSESSVLDHV0_LEN      1
#define SYSCTRL_CFG_OTGSESSVLDHV0_OFFSET   6
#define SYSCTRL_CFG_VBUSVALID0_LEN         1
#define SYSCTRL_CFG_VBUSVALID0_OFFSET      5
#define SYSCTRL_CFG_PHYCLOCK0_LEN          1
#define SYSCTRL_CFG_PHYCLOCK0_OFFSET       4

#define SYSCTRL_CFG_SC_NORESET_0_LEN    32
#define SYSCTRL_CFG_SC_NORESET_0_OFFSET 0

#define SYSCTRL_CFG_SC_NORESET_1_LEN    32
#define SYSCTRL_CFG_SC_NORESET_1_OFFSET 0

#define SYSCTRL_CFG_SC_NORESET_2_LEN    32
#define SYSCTRL_CFG_SC_NORESET_2_OFFSET 0

#define SYSCTRL_CFG_SC_NORESET_3_LEN    32
#define SYSCTRL_CFG_SC_NORESET_3_OFFSET 0

#define SYSCTRL_CFG_SC_NORESET_4_LEN    32
#define SYSCTRL_CFG_SC_NORESET_4_OFFSET 0

#define SYSCTRL_CFG_SC_NORESET_5_LEN    32
#define SYSCTRL_CFG_SC_NORESET_5_OFFSET 0

#define SYSCTRL_CFG_SC_NORESET_6_LEN    32
#define SYSCTRL_CFG_SC_NORESET_6_OFFSET 0

#define SYSCTRL_CFG_SC_NORESET_7_LEN    32
#define SYSCTRL_CFG_SC_NORESET_7_OFFSET 0

#define SYSCTRL_CFG_SC_NORESET_8_LEN    32
#define SYSCTRL_CFG_SC_NORESET_8_OFFSET 0

#define SYSCTRL_CFG_SC_NORESET_9_LEN    32
#define SYSCTRL_CFG_SC_NORESET_9_OFFSET 0

#define SYSCTRL_CFG_SC_NORESET_10_LEN    32
#define SYSCTRL_CFG_SC_NORESET_10_OFFSET 0

#define SYSCTRL_CFG_SC_NORESET_11_LEN    32
#define SYSCTRL_CFG_SC_NORESET_11_OFFSET 0

#define SYSCTRL_CFG_SC_NORESET_12_LEN    32
#define SYSCTRL_CFG_SC_NORESET_12_OFFSET 0

#define SYSCTRL_CFG_SC_NORESET_13_LEN    32
#define SYSCTRL_CFG_SC_NORESET_13_OFFSET 0

#define SYSCTRL_CFG_SC_NORESET_14_LEN    32
#define SYSCTRL_CFG_SC_NORESET_14_OFFSET 0

#define SYSCTRL_CFG_SC_NORESET_15_LEN    32
#define SYSCTRL_CFG_SC_NORESET_15_OFFSET 0

#define SYSCTRL_CFG_SYSCTRL_LOCK_LEN    32
#define SYSCTRL_CFG_SYSCTRL_LOCK_OFFSET 0

#define SYSCTRL_CFG_SYSCTRL_UNLOCK_LEN    32
#define SYSCTRL_CFG_SYSCTRL_UNLOCK_OFFSET 0

#define SYSCTRL_CFG_PROBE_MUX_SEL_LEN    3
#define SYSCTRL_CFG_PROBE_MUX_SEL_OFFSET 0

#define SYSCTRL_CFG_ECO_RSV0_LEN    32
#define SYSCTRL_CFG_ECO_RSV0_OFFSET 0

#define SYSCTRL_CFG_ECO_RSV1_LEN    32
#define SYSCTRL_CFG_ECO_RSV1_OFFSET 0

#define SYSCTRL_CFG_ECO_RSV2_LEN    32
#define SYSCTRL_CFG_ECO_RSV2_OFFSET 0

#define SYSCTRL_CFG_ECO_RSV3_LEN    32
#define SYSCTRL_CFG_ECO_RSV3_OFFSET 0

#define SYSCTRL_CFG_PROTOTYPE_CLK_LEN    32
#define SYSCTRL_CFG_PROTOTYPE_CLK_OFFSET 0

#define SYSCTRL_CFG_PROTOTYPE_RST_N_LEN    32
#define SYSCTRL_CFG_PROTOTYPE_RST_N_OFFSET 0

#define SYSCTRL_CFG_SC_SOFT_POR_RSV0_LEN    32
#define SYSCTRL_CFG_SC_SOFT_POR_RSV0_OFFSET 0

#define SYSCTRL_CFG_SC_SOFT_POR_RSV1_LEN    32
#define SYSCTRL_CFG_SC_SOFT_POR_RSV1_OFFSET 0

#define SYSCTRL_CFG_SC_SOFT_POR_RSV2_LEN    32
#define SYSCTRL_CFG_SC_SOFT_POR_RSV2_OFFSET 0

#define SYSCTRL_CFG_SC_SOFT_POR_RSV3_LEN    32
#define SYSCTRL_CFG_SC_SOFT_POR_RSV3_OFFSET 0

#define SYSCTRL_CFG_SC_MONITOR_TEST0_LEN    32
#define SYSCTRL_CFG_SC_MONITOR_TEST0_OFFSET 0

#define SYSCTRL_CFG_SC_MONITOR_TEST1_LEN    32
#define SYSCTRL_CFG_SC_MONITOR_TEST1_OFFSET 0

#define SYSCTRL_CFG_SC_VER_NUM_LEN    32
#define SYSCTRL_CFG_SC_VER_NUM_OFFSET 0

#endif // __SYSCTRL_CFG_REG_OFFSET_FIELD_H__
